1. Nectar F2F, Barcelona 2013-09 9/23/2015K.-H. Sulanke, DESY1 The Digital Trigger Backplane Rev. 2 power ethernet Frontend board connector L0 in /out and... connectors to neighbor clusters RJ-45 Xilinx FPGA vreg flash 24V ethernet power CLK PPS L0_trigger trigger IP_addr HV_ena SPI / JTAG calib_cyc reserved flash osc clock (opt.+power) PPS L1_trigger_out L2_trigger_in FE-board interface, compliant to FE_BP_interface_v6.doc by Gustavo M.

2. Nectar F2F, Barcelona 2013-09 9/23/2015K.-H. Sulanke, DESY2 Digital Trigger Backplane, cont. Clock_in PPS_in L1_out L2_in Hexadez. switches local clock osc. FE-board Gigabit ethernet FPGA PROM 24V Power DC-DC power supply Xilinx JTAG conn. 64 bit ID ROM FE-board connectors 50 pin flat cable Xilinx FPGA temp. sensor

3. Nectar F2F, Barcelona 2013-09 9/23/2015DESY3 The DTB-FPGA‘s Functionality delay 37 pixel trigger fabric fanout progr. delays PLL Xilinx Spartan 6 FPGA trigger pix_[0][6..0] pix_[1][4..0] pix_[6][4..0] clock from center cluster from surrounding clusters to surrounding clusters pix*_[0][4..0] calibrate STM to L2_trigger board FPGA

4. Nectar F2F, Barcelona 2013-09 9/23/2015K.-H. Sulanke, DESY4 Three New Boards Developed Digital Trigger Backplane L0 Mezzanine L0 Testboard

5. Nectar F2F, Barcelona 2013-09 9/23/2015K.-H. Sulanke, DESY5 The Cluster Service Board (CSB) Backplane connector Xilinx FPGA vreg flash 24V CLK PPS L2 L3 sdat JTAG Clock_PPS_24V GND L1_trigger L3_trigger RJ45 Cur_mon16 x switch 16 x Cat5e cables Clock PPS L1_trigger L3_trigger Or optional, including 24V

6. Nectar F2F, Barcelona 2013-09 9/23/2015K.-H. Sulanke, DESY6 The Centralized Trigger Schema with L2 L2 also based on Xilinx-Spartan 6 FPGAs L2 is a crate, ~ 50 x 20 x 20 cm, ~ 11 kg –18 x CSB (Cluster Service Board) –1 x L2CB (L2 Controller Board) Ethernet interface Optical / electrical camera trigger output PMT = Photomultiplier Tube FEB = Frontend Board DTB = Digital Trigger Backplane CSB = Cluster Service Board L2CB = L2 Controller Board L0 FEB DTB FPGA PMT L1 CSB L2 #01 … #16 L0 FEB FPGA L1 Sector_trig #01 … #18 FPGA Camera_trig GPS_clock PMT ethernet L2CB 77 7 7 L0_neighbor 24V (optional)