1. Team 2 Yimin Xiao Jintao Zhang Bo Yuan Yang

2.  The project we propose is a digital oscilloscope with playback function that provides almost any function of a typical oscilloscope, such as digital sampling, signal processing, auto-scale setting, cursor setting, reconstruction and visualization of signals. Additional features such as recording and replicating signals as a function generator, interacting with PC via USB and GUI display of signals will also be included.

3.  An ability to sample analog signal(-25V to 25V, with failsafe) at 500KHz sampling rate with 12Bit resolution  An ability to reconstruct and display the sampled signal on VGA display  An ability to create general oscilloscope interface and realize basic functions, such as auto/manual scale, quick measure, cursors, run/stop, and edge trigger  An ability to store/load the sampled signal to/from flash drive  An ability to reproduce the signal stored in external storage device and replay the signal on display

5.  Requirements ◦ ATD converter with 500KHz sampling frequency and 12 Bits resolution. ◦ PWM/DTA output data reconstruction. ◦ Operating frequency larger than 80MHz. ◦ On chip RAM to be larger than 128KB for signal processing data cache. ◦ On chip USB module. ◦ SPI/I 2 C bus interface to communicate with FPGA. ◦ Common voltage level as FPGA.

6.  Selections ◦ STM32F407VGT6  A/D Bit Size:12 bit A/D Channels Available:16  A/D Sampling Rate up to 2.4 MHz  D/A Bit Size:12 bit D/A Channels Available:2  Maximum Clock Frequency:168 MHz  Data RAM Size:192 KB  USB interface: USB 2.0 full-speed device/host  Interface Type: CAN, I2C, I2S, SPI, UART

7.  Selections ◦ LM4F232E5QC  A/D Bit Size:12 bit A/D Channels Available:24  A/D Sampling Rate up to 1 MHz  D/A Bit Size:32 bit D/A Channels Available:6  Maximum Clock Frequency:168 MHz  Data RAM Size: 32 KB  USB interface: USB 2.0 full-speed device/host  Interface Type: CAN, I2C, I2S, SPI, UART

8.  Requirements ◦ Low-cost PCI or SPI communication with MCU. ◦ VGA video output. ◦ System clocking frequency around same as MCU. ◦ Common voltage level as MCU. ◦ On-chip RAM for buffering the video output data.

9.  Selection ◦ Altera Cyclone II EP2C35  VGA Output Connector (J21)  3.3V/5V voltage tolerant  JTAG connected UART  100 MHz On-Board Oscillator ◦ Spartan-3E FPGA (XC3S500E-4FG320C)  33/66 MHz PCI interface  3.3V digital signal application  DDR SDRAM Memory Interface  5 MHz to 300 MHz system clock frequency range

10.  Voltage Divider ◦ MAX5490  Custom ratio from 1:1 to 1:100  Buffer ◦ LMH6703  +/-5V supply  Low Distortion  Input signal filter ◦ ELK-E333FA  Rated at 50V  Cutoff = 0.2 GHz