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November 2003 Michael Mc Laughlin, ParthusCeva Inc. Slide 1 doc.: IEEE 802.15-03a/0447r0 Submission Project: IEEE P802.15 Working Group for Wireless Personal.

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Presentation on theme: "November 2003 Michael Mc Laughlin, ParthusCeva Inc. Slide 1 doc.: IEEE 802.15-03a/0447r0 Submission Project: IEEE P802.15 Working Group for Wireless Personal."— Presentation transcript:

1 November 2003 Michael Mc Laughlin, ParthusCeva Inc. Slide 1 doc.: IEEE a/0447r0 Submission Project: IEEE P Working Group for Wireless Personal Area Networks (WPANs) Submission Title: Fast FIR Filter structure Date Submitted: 7 November 2003 Source: Michael Mc Laughlin, Roger Maher, Damien Nolan Company: ParthusCeva Inc. Address: Harcourt Street, Dublin 2, Ireland. Re: Fast FIR Filter structure Abstract: A Fast Finite Impulse response filter structure is analysed and gate counts are given for example implementations Purpose: Backup material for ParthusCeva/XSI/CRL TG3a PHY Proposal Notice: This document has been prepared to assist the IEEE P It is offered as a basis for discussion and is not binding on the contributing individual(s) or organization(s). The material in this document is subject to change in form and content after further study. The contributor(s) reserve(s) the right to add, amend or withdraw material contained herein. Release:The contributor acknowledges and accepts that these viewgraphs becomes the property of IEEE and may be made publicly available by P

2 November 2003 Michael Mc Laughlin, ParthusCeva Inc. Slide 2 doc.: IEEE a/0447r0 Submission FIR Gate count for example real and complex FIR implementations

3 November 2003 Michael Mc Laughlin, ParthusCeva Inc. Slide 3 doc.: IEEE a/0447r0 Submission Example Matched Filter Configuration CnCn DiDi C n+N D i-N 41 4x C n+1 D i-1 C n+N+1 D i-N x 44 4 bit adder 5 bit adder …..

4 November 2003 Michael Mc Laughlin, ParthusCeva Inc. Slide 4 doc.: IEEE a/0447r0 Submission Serial real FIR implementation FIR1 Input rate C*m Decimated Output rate C Filter rate C = 1368MHz Too fast C = chip rate m = over-sampling factor Real FIR allows up to 224Mbps

5 November 2003 Michael Mc Laughlin, ParthusCeva Inc. Slide 5 doc.: IEEE a/0447r0 Submission Parallel real FIR implementation FIR0FIR1FIR2FIRn … Input rate C*m Output rate C Filter rate C/n

6 November 2003 Michael Mc Laughlin, ParthusCeva Inc. Slide 6 doc.: IEEE a/0447r0 Submission RTL Synthesis summary Circuit synthesised in RTL using 130nm standard cell library, Worst case conditions Voltage, Temperature, Process. Average adder gate count per real adder = 34 Can be clocked at up to 193MHz –worst case conditions –full result available in a single cycle Used standard Ripple Carry adders Further speed optimisation possible e.g. –Introduce pipeline half way down adder tree ~ double speed, ~ half gate adder count, ~same power –fast adders –find your own ones!

7 November 2003 Michael Mc Laughlin, ParthusCeva Inc. Slide 7 doc.: IEEE a/0447r0 Submission Filter rate C=1368, m=4 n = 8 => Filter rate = 172MHz –(Synthesis shows 193MHz possible in 130nm) Taps per filter = 300 (Spread of 55ns) Total number of taps = n x 300 = 2400 No. 1 st stage pseudo-adders (or gates) = 1200 No. second stage adders (4 bit) = 600 No. of rest of adders (second up to last stage) = 600

8 November 2003 Michael Mc Laughlin, ParthusCeva Inc. Slide 8 doc.: IEEE a/0447r0 Submission Gate count Total no. adders = 1200 Average gates/adder = 34 – 20 gates for 4 bit adder –Bits per adder grows down the tree –Synthesis tools up drive strength, increasing gate count Total Adder Gates = 40,800 Other gates 8,600 Total gates = 49,400 No pipeline, 171MHz clock Total gates = 37,600 1 pipeline stage, 274 MHz clock

9 November 2003 Michael Mc Laughlin, ParthusCeva Inc. Slide 9 doc.: IEEE a/0447r0 Submission Serial complex FIR implementation FIR real Input rate C*m/2 real Decimated Output rate C (complex) Filter rate C C= 1368MHz - too fast C = chip rate m = over-sampling factor FIR imag FIR imag FIR real ++ Input rate C*m/2 imag

10 November 2003 Michael Mc Laughlin, ParthusCeva Inc. Slide 10 doc.: IEEE a/0447r0 Submission Parallel complex FIR implementation FIR 0 complex FIR 1 complex FIR 2 complex FIRn complex … Input rate C*m/2 complex Output rate C Filter rate C/n

11 November 2003 Michael Mc Laughlin, ParthusCeva Inc. Slide 11 doc.: IEEE a/0447r0 Submission Filter rate C=1368, m=4 n = 8 => Filter rate = 172MHz –(Synthesis shows 193MHz possible in 130nm) Taps per filter = 150 (Spread of 55ns) Total number of taps = 4 x n x 150 = 4800 No. 1 st stage pseudo-adders (or gates) = 2400 No. second stage adders (4 bit) = 1200 No. of rest of adders (second up to last stage) = 1200

12 November 2003 Michael Mc Laughlin, ParthusCeva Inc. Slide 12 doc.: IEEE a/0447r0 Submission Gate count Total no. adders = 2400 Average gates/adder = 34 (from synthesis results) –20 for 4 bit adder –Bits per adder grows down the tree –Synthesis tools up drive strength, increasing gate count Total Adder Gates = 81,600 Other gates 8,600 Total gates = 90,200 No pipeline, 171 MHz clock Total gates = 64,600 1 pipeline stage, 274MHz clock

13 November 2003 Michael Mc Laughlin, ParthusCeva Inc. Slide 13 doc.: IEEE a/0447r0 Submission Example bit rates


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