1. CIT 673 Created by Suriyong1 MCS51 ASSEMBLY Language Resources http://atmel.com/dyn/products/

2. CIT 673 Created by Suriyong2 Pin configuration

3. CIT 673 Created by Suriyong3 Block Diagram

4. CIT 673 Created by Suriyong4 Memory addresses with 5 address spaces Program memory/Code address space up to 64 K bytes Data Memory Directly addressable Normally 128 bytes low address (0-07FH) Expand to 256 bytes depend on CPU type (0-0FFH) Indirectly addressable for address 0-0x7f is the same page of direct address for 0x80-0xff is the another page External data address – up to 64K Bit address space same location to data memory address 0x20 – 0x2F 16 bytes: 128 bit address (0x00 – 0x7f)

5. CIT 673 Created by Suriyong5 Program memory address space 2 configuration controlled by /EA pin (External Address) Internal + external EA = “1” External Only EA = “0”

6. CIT 673 Created by Suriyong6 4 REGISTER BANKS RAM BIT ADDRESS SPACE ON-CHIP RAM HARDWARE REGISTER MAPPING NOT AVAILABLE FOR THE 8031 7070 255 127 47 31 DIRECTLY/INDIRECTLY ADDRESSABLE ON-CHIP RAM Internal data memory allocation Data Memory

7. CIT 673 Created by Suriyong7 Direct addressing area 2 pages : 128 bytes each lower area : 0x00-0x7f general purpose address 0x20 – 0x2F is bit addressable able to use both direct and indirect addressing mode higher area : 0x80 – 0xff with 2 pages 1 st page is conserved for SFR (Special Function Register) area use direct addressing mode 2 nd page is general purpose, access with indirect addressing

8. CIT 673 Created by Suriyong8 Basic internal data memory extra page of internal memory for other version of MCS51 (8052 etc): use indirect addressing mode

9. CIT 673 Created by Suriyong9 External data memory MCS51 able to expand the data memory called external data memory up to 64K bytes use both direct and indirect addressing mode not prefer when CPU operate in 1 chip mode

10. CIT 673 Created by Suriyong10 External data memory configuration MCS51 data memory, the external and internal are independent AT89S8252 PROGRAM MEMORY CONFIGURATION EXTERNAL DATA MEMORY CONFIGURATION

11. CIT 673 Created by Suriyong11 Bit addressable layout

12. CIT 673 Created by Suriyong12 The Registers locate at 0x80 – 0xff address except register R0-R7 at 4 banks of lower address 0x00 – 0x1f 2 type of register General Purpose registers Auxiliary/ Accumulator register (Acc or A) Multiplication/Scratch Pad Register (B) Stack pointer (SP) Data Pointer DPH/DPL -> DPTR Program Status Word – PSW Special Function Registers SBUF, SCON…TMOD Interrupt Enable/Priority (IE/ IP) Port register P0,P1,P2 and P3 etc. Both type bit addressable or not depend on register duty see more detail for each register

13. CIT 673 Created by Suriyong13 Register layout No name box is empty and conserve for future version

14. CIT 673 Created by Suriyong14 Register layout bit addressable display

15. CIT 673 Created by Suriyong15 General Purpose registers 8 registers with 4 banks 8 bytes/bank R0-R7 location 00H-1FH 4 banks selection controlled by RS0,RS1 bit in PSW often used in couple such as R0:R2, R1:R3 formed as 16 bit register

16. CIT 673 Created by Suriyong16 Stack Pointer (SP) initialize set to RAM location 07H Last In First Out (LIFO) mechanism store Program Counter, PSW etc. not exceed 127 increment when use

17. CIT 673 Created by Suriyong17 PSW – Program Status Word For operation checking or status such as carry flag, overflow flag Status for ALU operation

18. CIT 673 Created by Suriyong18 The SFR Port: P0 – P3 perform 32 bit addressable independent I/O port Timer/Counter : T0 – T2 8 bit, timer/counter with internal/external input SBUF, SCON Serial communication buffer and control etc.

19. CIT 673 Created by Suriyong19 Instruction group of MCS51 assembly language Operation Arithmetic logical boolean Data transfer Program control

20. CIT 673 Created by Suriyong20 Arithmetic operation Effect PSW register OV, CY and AC flag Command set ADD, ADDC : ADD, with Carry SUB, SUBB : SUBtract, with Borrow MUL : Register Multiplication DIV : Register Division INC : Increment DEC : Decrement DAA : Decimal Adjust example ADDC A, #07FH ; add register a with 07f and carry and ; store in A Question: Show the event that effect OV, CY and AC

21. CIT 673 Created by Suriyong21 Logical Operation ANL : AND with accumulator ORL : logical OR with accumulator XRL : logical XOR with accumulator CLR : CLeaR accumulator to zero CPL : Complement RL, RLC : Rotate Left, with Carry flag RR, RRC : Rotate Right, with Carry flag SWAP : Swap nibble within accumulator

22. CIT 673 Created by Suriyong22 Boolean Manipulation manipulate bit or flag use Carry flag as bit accumulator CLR C, bit; clear carry or bit SETB C or bit; set carry or bit to “1” CPL C or bit, bit complement ANL C, bit; C=C and bit ORL MOV C, bit; move with carry

23. CIT 673 Created by Suriyong23 Data transfer MOV A, ; copy with Accumulator MOVC A, ; move code with acc MOVX A, ; move external with ; acc PUSH & POP ; push and pop to stack XCH A, ; exchange with acc XCHD A, Rn ; exchange register with A, ; low nibble digit

24. CIT 673 Created by Suriyong24 Machine control Jump with condition JZ/JNZ ; Jump if Zero flag/non zero flag JC/JNC ; Jump if carry flag/non carry flag JB/JNB direct; Jump if direct bit/not direct bit CJNE ; compare jump if not equal DJNZ; Decrement and Jump if non zero no condition AJUP/LJMP/SJMP JMP @A+DPTR ; jump indirect CALL ACALL, LCALL with 11bit, 16 bit address Return RET ; return RETI ; return from interrupt NOP ; no operation

25. CIT 673 Created by Suriyong25 The addressing mode Register addressing source can be either register R0 – R7 MOV A, R0 Direct addressing Source is represented with memory location MOV A, 07FH Indirect source is register and its content is index point to the data location source is used together with “@” sign MOV A, @R0; copy to A with the content of R0 point to Immediate source is numeric value precede with “#” sign MOV A, #07FH

26. CIT 673 Created by Suriyong26 Indirect Addressing register contain the address of memory instead normally affect the on-chip RAM use at sign “@” in the instruction example MOV A, @Rn MOV @Rn, #07fh

27. CIT 673 Created by Suriyong27 Bit Addressing affect the bit addressable area may name or define the bit address eg. SETB TR1 ; set bit Timer reset of Timer1 SETB 88H.6; set the bit at address 88H bit 6

28. CIT 673 Created by Suriyong28 For external data memory Indirect access only Use with data transfer instruction group add C for Code, X for external data memory to the operation Use register DPTR (DPH:DPL) for point to either code and data example MOVX A, @DPTR; MOVX A, @A+DPTR; move the content the dptr is point to register A MOVC A, @A+DPTR

29. CIT 673 Created by Suriyong29 Instruction Summary ARITHMETIC OPERATIONS ADDA,RnAdd register to Accumulator ADDA,directAdd direct byte to ADDA,@RiAdd indirect RAM to Accumulator ADDA,#dataAdd immediate data to Accumulator ADDCA,RnAdd register to Accumulator with Carry ADDCA,directAdd direct byte to Accumulator with Carry ADDCA,@RiAdd indirect RAM to Accumulator with Carry ADDCA,#dataAdd immediate data to Acc with Carry SUBBA,RnSubtract Register from Acc with borrow SUBBA,directSubtract direct byte from Acc with borrow SUBBA,@RiSubtract indirect RAM from ACC with borrow SUBBA,#dataSubtract immediate data from Acc with borrow INCAIncrement Accumulator INCRnIncrement register INCdirectIncrement direct byte INC@RiIncrement direct RAM DECADecrement Accumulator DECRnDecrement Register DECdirectDecrement direct byte DEC@RiDecrement indirect RAM INCDPTRIncrement Data Pointer MULABMultiply A & B DIVABDivide A by B DAADecimal Adjust Accumulator LOGICAL OPERATIONS ANLA,RnAND Register to Accumulator ANLA,directAND direct byte to Accumulator ANLA,@RiAND indirect RAM to Accumulator ANLA,#dataAND immediate data to Accumulator ANLdirect,AAND Accumulator to direct byte ANLdirect,#dataAND immediate data to direct byte ORLA,RnOR register to Accumulator ORLA,directOR direct byte to Accumulator ORLA,@RiOR indirect RAM to Accumulator ORLA,#dataOR immediate data to Accumulator ORLdirect,AOR Accumulator to direct byte ORLdirect,#dataOR immediate data to direct byte XRLA,RnExclusive-OR register to Accumulator XRLA,directExclusive-OR direct byte to Accumulator XRLA,@RiExclusive-OR indirect RAM to Accumulator XRLA,#dataExclusive-OR immediate data to Accumulator XRLdirect,AExclusive-OR Accumulator to direct byte XRLdirect,#dataExclusive-OR immediate data to direct byte CLRAClear Accumulator CPLAComplement Accumulator RLARotate Accumulator Left RLCARotate Accumulator Left through the Carry RRARotate Accumulator Right RRCARotate Accumulator Right through the Carry SWAPASwap nibbles within the Accumulator DATA TRANSFER MOVA,RnMove register to Accumulator MOVA,directMove direct byte to Accumulator MOVA,@RiMove indirect RAM to Accumulator MOVA,#dataMove immediate data to Accumulator MOVRn,AMove Accumulator to register MOVRn,directMove direct byte to register MOVRn,#dataMove immediate data to register MOVdirect,AMove Accumulator to direct byte MOVdirect,RnMove register to direct byte MOVdirect,directMove direct byte to direct MOVdirect,@RiMove indirect RAM to direct byte MOVdirect,#dataMove immediate data to direct byte MOV@Ri,AMove Accumulator to indirect RAM MOV@Ri,directMove direct byte to indirect RAM MOV@Ri,#dataMove immediate data to indirect RAM MOVDPTR,#data16 Load Data Pointer with a 16-bit constant MOVCA,@A+DPTRMove Code byte relative to DPTR to Acc MOVCA,@A+PCMove Code byte relative to PC to Acc MOVXA,@RiMove External RAM (8-bit addr) to Acc MOVXA,@DPTRMove External RAM (16-bit addr) to Acc MOVX@Ri,AMove Acc to External RAM (8-bit addr) MOVX@DPTR,AMove Acc to External RAM (16-bit addr) PUSHdirectPush direct byte onto stack POPdirectPop direct byte from stack XCHA,RnExchange register with Accumulator XCHA,directExchange direct byte with Accumulator XCHA,@RiExchange indirect RAM with Accumulator XCHDA,@RiExchange low-order Digit indirect RAM with Acc BOOLEAN VARIABLE MANIPULATION CLRCClear Carry CLRbitClear direct bit SETBCSet Carry SETBbitSet direct bit CPLCComplement Carry CPLbitComplement direct bit ANLC,bitAND direct bit to CARRY ANLC,/bitAND complement of direct bit to Carry ORLC,bitOR direct bit to Carry ORLC,/bitOR complement of direct bit to Carry MOVC,bitMove direct bit to Carry MOVbit,CMove Carry to direct bit JCrelJump if Carry is set JNCrelJump if Carry not set JBbit,relJump if direct Bit is set JNBbit,relJump if direct Bit is Not set JBCbit,relJump if direct Bit is set & clear bit PROGRAM BRANCHING ACALLaddr11Absolute Subroutine Call LCALLaddr16Long Subroutine Call RETReturn from Subroutine RETIReturn from interrupt AJMPaddr11Absolute Jump LJMPaddr16Long Jump SJMPrelShort Jump (relative addr) JMP@A+DPTRJump indirect relative to the DPTR JZrelJump if Accumulator is Zero JNZrelJump if Accumulator is Not Zero CJNEA,direct,relCompare direct byte to Acc and Jump if Not Equal CJNEA,#data,relCompare immediate to Acc and Jump if Not Equal CJNERn,#data,relCompare immediate to register and Jump if Not Equal CJNE@Ri,#data,relCompare immediate to indirect and Jump if Not Equal DJNZRn,relDecrement register and Jump if Not Zero DJNZdirect,relDecrement direct byte and Jump if Not Zero NOPNo Operation

30. CIT 673 Created by Suriyong30 Application with SFR I/O PORT TIMER/Counter Serial communication Interrupt control

31. CIT 673 Created by Suriyong31 Port P0 – P3 4 Ports, 32 bits all bits can assign as input/output independently, alternate function P0: address (a0-a7) bus/data bus P2: high address (a8-a15) bus P3: control and i/o of Timer/counter and interrupt

32. CIT 673 Created by Suriyong32 Timer/counter 2 timer (timer0 and time1) for standard, the same structure SFR TCON and TMOD container is TH:TL 3 mode able to use interrupt

33. CIT 673 Created by Suriyong33 Mode 0:13 bit timer/counter Mode 1: 16 bit timer/counter

34. CIT 673 Created by Suriyong34 Mode 2: 8 bit auto reload

35. CIT 673 Created by Suriyong35 TMOD & TCON

36. CIT 673 Created by Suriyong36 Serial communication MCS51 provide serial communication channel component need timer for communication clock (timer 1 auto reload mode) tx : transmit channel and rx : receive channel control register SCON: serial control content register SBUF : data transmit or receive at SBUF register

37. CIT 673 Created by Suriyong37 SCON: Serial Control Register

38. CIT 673 Created by Suriyong38 Baud rate generating

39. CIT 673 Created by Suriyong39 Assembly example Two Byte Decimal Add with Registers and Constants ; BCDADD ADD THE CONSTANT 1,234 (DECIMAL) TO THE ; CONTENTS OF REGISTER PAIR (R3)(R2) ;(ALREADY A 4 BCD-DIGIT VARIABLE) ; BCDADDMOVA, R2 ADDA, #34H DAA MOVR2, A MOVA, R3 ADDCA, #12H DAA MOVR3, A RET

40. CIT 673 Created by Suriyong40 Case Statements Using CJNE CHAREQUR7; CHARACTER CODE VARIABLE ; INTERPCJNECHAR, #7FH, INTP_1 ;(SPECIAL ROUTINE FOR RUBOUT CODE) RET INTP_1CJNECHAR, #07H, INTP_2 ;(SPECIAL ROUTINE FOR BELL CODE) RET INTP_2CJNECHAR, #0AH, INTP_3 (SPECIAL ROUTINE FOR LFEED CODE) RET INTP_3CJNECHAR, #0DH, INTP_4 (SPECIAL ROUTINE FOR RETURN CODE) RET INTP_4CJNECHAR, #1BH, INP_5 (SPECIAL ROUTINE FOR ESCAPE CODE) RET INTP_5CJNECHAR, #20H, INTP_6 (SPECIAL ROUTINE FOR SPACE CODE) INTP_6JCPRINTC; JUMP IF CODE > 20H MOVCHAR, #0; REPLACE CONTROL CHARACTERS WITH ; NULL CODE PRINTC; PROCESS STANDARD PRINTING CHARACTER RET

41. CIT 673 Created by Suriyong41 Implementation of Boolean function

42. CIT 673 Created by Suriyong42 Interrupt program program that interrupt the main program ask for service routine 2 source of interrupt internal such as activate by timer overflow flag external signal source when interrupting happen program counter is load with corresponding address the address contain interrupt vector point to the routine

43. CIT 673 Created by Suriyong43 concerned register

44. CIT 673 Created by Suriyong44 interrupt source and default value default priority IE0, TF0, IE1, TF1, RI OR TI source address interrupt architecture

45. CIT 673 Created by Suriyong45 References Wharton, J., An Introduction to the Intel MCS-51 Single-chip Microcontroller family, Application Notes, AP-69, May 1980, pdf document 01502a01.pdf MCS51 microcontroller family user manual, February 1994 8-bit micro controller with 8 k bytes flash, Atmel 89s8252 data sheet, doc0401.pdf