2. Chapter 3 By James Hanson June 2002

3. DRAM Dynamic-RAM Needs to be refreshed every few milliseconds 1 Transistor/ 1 Capacitor

4. SRAM Static-RAM Doesn’t need to be refreshed. Keeps memory as long as it has power. 6 Transistors

5. Cache A type of fast memory. Located in or near the CPU. Doesn’t need to be refreshed. Types L1, L2-[Discrete/ATC], and COAST. Static memory.

6. L1 Cache Level 1 Cache located closest to the processor. Internal Cache.

7. L2 Cache Level 2 External cache located near the processor as in Discrete and ATC. Or close to the CPU like COAST.

8. Discrete Cache Cache that is in the CPU package. Connected to the processor by a bus. Pentium Pro was first chip to use.

9. ATC Advance Transfer Cache Cache that is embedded in the processor section of the CPU. Fastest L2 cache.

10. C.O.S.T Cache On a Stick. External Cache on main board. Connect via memory bus. Slowest cache.

11. Backside Bus The bus that connects the L2 discrete cache to the processor. Run at ½ to full speed of processor.

12. Frontside Bus Bus out of the CPU to the system board. Also Known as the memory bus or system bus. Speed varies by chip set, CPU, and Moterboard.

13. Local Bus A bus that is synchronized with CPU. Northbridge and above.

14. External Bus A bus that runs asynchronies of the CPU. Below the Northbridge.

15. Wait state When the CPU must pause and wait for slower devices.

16. RISC Reduced Instruction Set Computer. Sends fewer/simpler instructions by using the most frequently used ones. Faster then CISC

17. CISC Complex Instruction Set Computer. More complex/ complete instructions are sent therefore it is slower.

18. CPU Form Factors Also known as sockets and slots. PGA and SPGA SEP, SECC, SECC2, PPGA, and FC-PGA.

19. PGA Pin Grid Array Pins are aligned in uniform rows around the socket. Sockets 4 and 6

20. SPGA Staggered Pin Grid Array Pins are place in a staggered pattern on the package to get more on. Sockets include 5,7, super 7, 8, and 370 Socket 7 run at 66 MHz Super 7 runs at 100 MHz and supports AGP and uses AMD chips vs. Intel.

21. SEP Single Edge Processor Is not covered in plastic case. The first Celerons were this way. Fits Slot 1

22. SECC Single Edge Contact Cartridge Covered completely in in a plastic housing. Pentium II and Pentium III may use Slot 1.

23. PPGA Plastic Pin Grid Array Processor is in a flat square box made to fit a Socket 370. Fan and heat sink attach to top with a heat spreader or thermal plate. New Celerons come this way.

24. FC-PGA Flip Chip Pin Grid Array Looks like PPGA and also uses Socket 370. Heat sink and fan attach directly to the top of CPU. Pentium III also come this way.

25. AGP Accelerated Graphics Port System boards have one AGP slot that is more of a port then a bus. Has direct access to the CPU, rather then routing through the slower PCI bus. 66-MHz – 32-bit AGP 2X /AGP 4X

26. ISA Industry Standard Architecture First came out in 8-bit bus later IBM extended to 16-bit. 8-MHz

27. MCA Microchannel Architecture Introduced by IBM in 1987 for a short time First 32-bit bus Replaced by PCI

28. PCI Peripheral Component Interconnect bus Has become the standard for I/O bus 33-MHz/66-MHz - 32-bit PCI-X 66-MHz/133-MHz - 64-bit

29. AMR Audio Modem Riser Designed for small, cheap cards. Most of the logic for the audio or modem is supported by the system board chip set. Cheap way to expand with out ISA/PCI.

30. USB Universal Serial Bus Is replacing parallel and serial ports. Easy installation of I/O devices through Plug-N- Play. Able to use up 127 devices on one IRQ Enables Hot-Swapping USB 1 speeds of 1.5 Mbs – 12 Mbs USB 2 speeds up to 480 Mbs

31. FireWire Expansion bus that can configured as a local bus. It may replace SCSI in the future. Used for fast I/O devices. Also called IEEE 1394 and I.link Up to 63 devices per channel. Speeds up to 400 Mbs

32. Push Me