1. 2007 Sept 06SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt1 Computer Architecture & Organization  Instruction set, number of bits used for data representation, I/O mechanisms, addressing techniques, etc.  e.g. Is there a multiply instruction?  Control signals, interfaces, memory technology, etc.  e.g. Is there a hardware multiply unit or is it done by repeated addition? hmmm … chicken/egg problem ? Architecture  attributes visible to the programmer Organization  how features are implemented

2. 2007 Sept 06SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt2 What Should I already know re Computer Arch & Org ? computer keyboard mouse display disk / optical speakers other ?...... connected devices Peripherals printer communication links network telephone cable wireless other ?...... “Black Box” !

3. 2007 Sept 06SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt3 Function & Structure  SYSC 2001 will look inside the black box (ITBB)! peripherals and comm n links are outside black box Will construct various models of ITBB components:  Function  the operation of individual components as parts of the structure  Structure  how components relate to each other ITBB

4. 2007 Sept 06SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt4 Function  ALL computer functions are: Data PROCESSING Data STORAGE Data MOVEMENT CONTROL  NOTHING ELSE! Data = Information Coordinates How Information is Used IMPORTANT SLIDE !

5. 2007 Sept 06SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt5 Functional view of Black Box Operating Environment source/sink for information MOVEMENT CONTROL PROCESSING STORAGE connections to peripherals and comm n links ITBB

6. 2007 Sept 06SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt6 Operations (1) Data movement e.g. copy a file between disks

7. 2007 Sept 06SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt7 Operations (2) Storage e.g. load a text file for editing

8. 2007 Sept 06SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt8 Operation (3) Processing from/to storage e.g. compute an intermediate result from some operands & save for later use

9. 2007 Sept 06SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt9 Operation (4) Processing from storage to I/O e.g. compute and display a result from some operands

10. 2007 Sept 06SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt10 Structure - Top Level ITBB Computer Main Memory Input Output Systems Interconnection Peripherals Communication lines Central Processing Unit Computer What about Function? More Black Boxes ITBB!

11. 2007 Sept 06SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt11 Structure - The CPU Computer Arithmetic and Logic Unit Control Unit Internal CPU Interconnection Registers CPU I/O Memory System Bus CPU What about Function? Drilling Down I(ITBB)!

12. 2007 Sept 06SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt12 Structure - The Control Unit CPU Control Memory Control Unit Registers and Decoders Sequencing Logic Control Unit ALU Registers Internal Bus Control Unit What about Function? Too deep for SYSC 2001

13. 2007 Sept 06SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt13 Brief History of Computer Evolution Two phases: 1.before VLSI1945 – 1978 ENIAC IAS IBM PDP-8 2.VLSI 1978  present day microprocessors ! see text discussion VLSI = Very Large Scale Integration

14. 2007 Sept 06SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt14 Growth in CPU Transistor Count Moore’s Law Pentium Evolution PowerPC Evolution Cell 234 M

15. 2007 Sept 06SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt15 Speeding Up the Processor  Pipelining  On board cache  On board L1 & L2 cache  Branch prediction  Data flow analysis  Speculative execution chicken / egg again ! we’ll see some of these as the course progresses

16. 2007 Sept 06SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt16 But Performance Mismatch!  Processor speed increased  Memory capacity increased  Memory speed lags behind (and increasing slower than) processor speed

17. 2007 Sept 06SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt17 DRAM and Processor Characteristics

18. 2007 Sept 06SYSC 2001* - Fall 2007. SYSC2001-Ch1.ppt18 Some Solutions  Increase number of bits retrieved at one time Make DRAM “wider” rather than “deeper”  Change DRAM interface Cache  Reduce frequency of memory access More complex cache, and cache on chip  Increase interconnection bandwidth High speed buses Hierarchy of buses