2. © 2000 Morgan Kaufman Overheads for Computers as Components Instruction sets zComputer architecture taxonomy. zAssembly language. ARM processor  PDA’s, video games, telephones SHARC  DSP

3. © 2000 Morgan Kaufman Overheads for Computers as Components von Neumann architecture zMemory holds data, instructions. zCentral processing unit (CPU) fetches instructions from memory. ySeparate CPU and memory distinguishes programmable computer. zCPU registers help out: program counter (PC), instruction register (IR), general- purpose registers, etc.

4. © 2000 Morgan Kaufman Overheads for Computers as Components CPU registers zProgram counter (PC): z bit-width represents processor’s address size zaddress size M  address space =? zPC holds next instruction z Instruction Register (IR): z holds fetched instruction zOther registers serve as processor’s short- term memory (index register, accumulator, status register, …)  fast access time compared to external memory

5. © 2000 Morgan Kaufman Overheads for Computers as Components CPU + memory Memory CPU PC Address bus Data bus IR ADD r5,r1,r3 200 ADD r5,r1,r3 Program Counter

6. © 2000 Morgan Kaufman Overheads for Computers as Components Harvard architecture CPU PC data memory program memory address data address data Points to Program memory- Not data memory

7. © 2000 Morgan Kaufman Overheads for Computers as Components von Neumann vs. Harvard zHarvard allows two simultaneous memory fetches: DATA & PROGRAM zMost DSPs use Harvard architecture for streaming data: ygreater memory bandwidth; yData and program do not compete for the same port (Telephone calls  speech processing  DSP)

8. © 2000 Morgan Kaufman Overheads for Computers as Components RISC vs. CISC zEarly computers: Complex instruction set computer (CISC): ymany addressing modes; ymany operations, e.g., string search, division, block transfer, … zReduced instruction set computer (RISC): yload/store; ypipelinable instructions. z Question: Any advantage of using RISC vs CISC?

9. © 2000 Morgan Kaufman Overheads for Computers as Components Instruction set characteristics zFixed vs. variable length instructions. zAddressing modes: Immediate, register addressing (direct: for regular variables, indirect: to implement pointers), implicit addressing (accumulator), relative, … zNumber of operands. zTypes of operands.

10. © 2000 Morgan Kaufman Overheads for Computers as Components Programming model zProgramming model: Set of registers visible to the programmer and available for use. zSome registers are not visible (IR).

11. © 2000 Morgan Kaufman Overheads for Computers as Components Selecting a processor: Achieve a desired speed with certain power/cost requirements zClock speed zNumber of instructions per clock cycle is different among processors zInstructions per second (MIPS) zComplexity of instructions may be different (for the same function one my require less instructions) zDhrystone benchmark: C program to exercise processor’s integer arithmetic and string handling speed zVAX 11/780 executes 1757 Dhrystones/sec ( 1MIPS machine) zNumber of Dhrystones/sec is compiler dependent

12. © 2000 Morgan Kaufman Overheads for Computers as Components Assembly language: Textual description  Binary representation zBasic features: yOne instruction per line. yLabels provide names for addresses (usually in first column). yInstructions often start in later columns. yColumns run to end of line.

13. © 2000 Morgan Kaufman Overheads for Computers as Components ARM assembly language example label1ADR r4,c LDR r0,[r4] ; a comment ADR r4,d LDR r1,[r4] SUB r0,r0,r1 ; comment Address or memory location [c] – [d]

14. © 2000 Morgan Kaufman Overheads for Computers as Components SHARC assembly language zAlgebraic notation terminated by semicolon: R1=DM(M0,I0), R2=PM(M8,I8);!comment label: R3=R1+R2; data memory access program memory access DAG1 and DAG2 registers

15. © 2000 Morgan Kaufman Overheads for Computers as Components Pseudo-ops zSome assembler directives don’t correspond directly to instructions: yDefine current address. yReserve storage. yConstants. NEXT ARM assembly language