1. “ Analyzer for 40Gbit Ethernet “ (Bi-semestrial project) Executers: פריד מחאג ' נה 200619716 Farid Mahajna Husam Kadan חוסאם קעדאן 301461703 Instructor: Mony Orbach Starting at semester: winter 2010/2011 Date: 15-11-2010

2. Agenda What is a communication channel ? Our projects goals Work environment Development – High level architecture Development – Testing Evironment Gantt Chart Questions

3. Communication Channel A channel is used to convey an information signal, for example a digital bit stream, from one or several senders (or transmitters) to one or several receivers. Com. Channels are everywhere. Two important parameters:  speed  bandwidth

4. What is the final Goal ? Two stages: 1. Building the physical layer (first semester) o Reaching a point we can send and receive data 2. Implements Ethernet protocol (second semester) “Building a high speed communication channel - 40Gbit”

5. Work Environment Hardware side:  Virtex-6 FPGA ML605 Evaluation Kit – the board  Mezzanine Card  Ethernet Protocol  Aurora  SerDes Software side (tools):  ISE 12.3 version

6. Work Environment FPGA The mezzanine card sets here (HPC inputs) DDR Virtex-6 FPGA ML605 Evaluation Kit

7. Mezzanine Card Work Environment

8. A Serializer/Deserializer (SerDes) is a pair of functional blocks commonly used in high speed communications to compensate for limited input/output. These blocks convert data between serial data and parallel interfaces in each direction. One By One

9. Aurora Aurora takes a data packet (Bit stream) and divide it into several synchronized parallel channels. Aurora is a block in the ISE library. This is one of the most important parts of our project.

10. Development High level architecture on the FPGA Transmitterreceiver MEM MEM MNG Aurora Physical layer SerDes

11. Development Testing Env. - 2 Ports Testing Env. - One Port The Board FPGA The Board FPGA Mezzanine Card Output Pin Input Pin Starting with one port channel… SMA Connectors

12. Board A Board B Mezzanine Card FPGA …ending with 4 parallel Development Testing Env. - 4 parallel ports FPGA

13. Gantt Chart (Till the middle of the semester)

14. Questions