1. 10101011 MSBLSB A byte comprises eight bits. The number shown above is a binary number, which is one byte in length. The rightmost 1 st bit, i.e., is known as the Least Significant Bit (LSB) and the leftmost 8 th bit, i.e., is called the Most Significant Bit (MSB) of the byte.

2. Decimal number 2 2 7 5 2 0 9 6 1 0 0 0 1 0 1 1 Binary number Decimal Weight Binary Weight (a) (b) A decimal number has base 10 (ten), whereas a binary number has base 2 (two). Similar to the decimal number system, each position of a binary number comprised of bit streams has a unique weight. The weight of each position is calculated in terms of ‘power over two.’ For instance, the weight of bit position 5 i.e., is = 16.

3. 4 2 6 7 1 0 0 3 Octal weight The octal number system uses 8 as its base and accommodates digits 0, 1, 2, 3, 4, 5, 6 and 7. The weight of each position is determined similar to decimal and binary number systems

4. 4 2 6 7 100 010 110 111 = (100010110111) 2 Octal number In this figure the given octal number is (4267) 8. Its binary equivalent is (100010110111) 2, which is a 12 bit binary number. Octal to binary conversion

5. (1110010001011101) 2 Start making group from least significant bit 001 110 010 001 011 101 1 6 2 1 3 5 = (162135) 8 To convert binary to octal number, simply break the binary number into a group of three bits, starting from the least significant bit. Then convert the 3-bit binary number to its octal equivalent. Binary to Octal conversion

6. (b) A 1 4 9 0 F 6 2 Hexadecimal weight Hexadecimal number The hexadecimal number system is derived from four-bit binary numbers. This number system can be used to represent the same values as the decimal and binary number systems. Just like the decimal number system represents a power of 10, each hexadecimal number represents a power of 16

7. (b) (10001101) 2 Start making group from least significant bit (F10A) 16 1111 0001 0000 1010 = (1111000100001010) 2 8 D = (8D) 16 1000 1101 (a) Similarly, to convert binary to hexadecimal, break the binary number into a group of four bits, starting from the least significant bit. Convert the 4-bit binary number to its hexadecimal equivalent.

8. 0011 0110 0001 0000 1001 = ( 0011 0110 0001 0000 1001) BCD 100011010101011100 Start making group from least significant bit (a) (b) 3 6 1 0 9 0100 1000 0000 0011 4 8 0 3 (4803) 10 Decimal The BCD number system has ten combinations of nibble (a group of 4-bit is called a nibble) corresponding to each decimal number. The conversion of decimal to BCD or BCD to decimal is similar to the conversion of hexadecimal to binary and vice versa. To convert from BCD to decimal, just reverse the process.

9. P-0 p-1 p-2 p-3 p-4 p-5 p-6 p-7 p-8 p-9 Output of the sensor providing binary code Output of the sensor providing Gray code A typical example of a position detection system using gray code. A change in adjacent location only affects one bit for a Gray code pattern, whereas using a binary code pattern up to four bits could change, giving rise to wildly incorrect readings.

10. 1 + 0 0 + 0 0 + 1 1 + 1 1 + 1 Carry nil Rule-5Rule-4Rule--3Rule-2Rule-1 Carry nil Carry ‘1’ 0111011 The following fundamental rules are employed in adding binary numbers. (Also refer Figure-4.10) 0 + 0 = 0 (carry nil) 0 + 1 = 1 (carry nil) 1 + 0 = 1 (carry nil) 1 + 1 = 10 (carry 1) 1 + 1 + 1 = 11 (carry 1)

11. +5 volts - 5 volts 1 1 1 0 0 +5 volts 0 volts - 5 volts 0 volts 1 1 1 0 0 1 1 1 0 0 Theoretically and numerically these two logic states are expressed as ‘1’ or ‘0’ and electrically they are realized as V and or vice versa, where and essentially are two distinct voltage levels. If V represents ‘1,’ then has to represent ‘0’ or vice versa. Positive logic: Higher voltage represents ‘1’ and the lower voltage represents ‘0’ Negative logic: Lower voltage represents ‘1’ and the higher voltage represents ‘0’

12. AND ABCABC ABCABC YY OR AY NOT (b) A B C Y A B C Y A Y 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 0 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 1 (e) (a) (c) (d)(f) The basis of logic circuits are logic functions. Basic logic functions are OR, AND and NOT. These logic functions are in fact realized by means of solid state electronics, which in turn are defined as Logic Gates. In view of that there are three logic gates such as OR gate, AND gate and NOT gate. Logic gates, circulating the fundamental principle of logic functions, constitute the functional building blocks in designing the digital circuits or digital system.

13. ABCDABCD Using the variables, A, B, C, D, and Y, the truth table of this gate is shown in the figure.

14. B C E input Output Common-emitter configuration n-p-n +5 volts 1 (5 volts) 0 (0 volts) R The simplest gate is an inverter or NOT gate. It takes a bit or state as input and produces its opposite as output. If the input is ‘0,’ the output is ‘1’. If the input is ‘1’ then the output is ‘0.’ NOT gates can be realized using a transistor.

15. Y (b) ABCABC OR Y NOT AND ABCABC NAND Y ABCABC Y NOT NOR ABCABC OR (a) A B C Y 0 0 0 1 0 0 1 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 Symbol A B C Y 0 0 0 1 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 1 0 0 1 1 1 0 Figure (a) describes three input NAND gate and its truth table. Figure (b) describes a NOR gate and its truth table. From the figure is it appropriate to say OR-NOT and AND- NOT rather than NOT-OR and NOT-AND, respectively.

16. NOT AND OR Y A B NOT AND Y ABAB SymbolXOR XOR Truth table A B Y 0 0 0 0 1 1 1 0 1 1 1 0 “ The XOR gate output is ‘1’ if any one of the inputs are ‘1’; the output is ‘0’ when all inputs are ‘0’ or ‘1’.” The notation is used to describe the operation. It narrates that “Y is exclusively A or B”.

17. Y SUM ABAB SymbolXOR CARRY BIT C Half-adder truth table with carry A B C Y 0 0 0 1 1 0 0 1 1 1 1 0 An XOR gate is called a half-adder electronic circuit. One can see from the rows of the truth table that the gate adds two input bits.

18. S R Y 0 0 No change 0 1 0 1 0 1 1 1 Not allowed S R Y 0 0 Not allowed 0 1 1 1 0 0 1 1 No change Y Y SRSR SR flip-flops using NAND gates SRSR SR flip-flops using NOR gates (a) (b)(c) SRSR Clock Y A simple type of flip-flop that can retain or store a single bit is an SR flip-flop. S stands for ‘set’ and R stands for ‘reset.’ The truth table of an SR flip-flop is given. (b) illustrates the realization of SR flip-flops using NAND and NOR gates. (c) is its symbol. Although the SR flip-flop behaves as a single bit memory cell but they can be used for sequencing and triggering applications.

19. SRSR Clock Y SRSR The clock input given to the SR flip-flop is to sequence the operation in terms of displaying the next-time status of the circuit.

20. T-1 T-2 S R ABY Although SR flip- flops are realized either using NAND gates or NOR gates, in their basic form the SR circuit is simply two transistors connected back to back as shown. As soon as the terminals S and R are made high one would saturate (go to active reason) faster than the other. There would be a race between the two transistors so connected.

21. Clock D Y 0 0 No change 0 1 No change 1 0 0 1 1 1 Clock Y SRSR D (a)(b) (c) Symbol D Clock Y The SR flip-flop can retain a bit at the output Y in response to setting and resetting of input. In essence, once a bit is retained it is memorized. This retaining ability of the flip- flop forms the basis in designing real memory devices. Indeed, several flip-flops are put together to store large set of DNS data. Some of the flip-flops are very good as far as design of real memory devices are concerned. D flip-flops are good in this respect.

22. v v J K Y Clock SRSR (c) Symbol J Clock Y K (a) (b) A JK flip-flop is one of the most versatile flip- flop and frequently used in digital control systems. It has two data inputs like an SR flip-flop and a clock input. The two data inputs are called the J and K terminals. It does not inherit the race problem.

23. D Clock D D D D D D D INPUT OUTPUTOUTPUT (a) (b) OUTPUT INPUT Time pulses Time A large memory block is composed of a set of many small units called registers.

24. Y OUTPUTOUTPUT Group-1 Group-2 ENABLE Multiplexers are sequential logical devices used for various applications such as data selector, data multiplexing, and even for the genera- tion of Boolean functions.

25. A B C D BC AD CD A+B (A+B)+BC+AD+CD A truth table could have more than one Boolean expression. Boolean expression contains redundant terms. So minimisation is necessary. The truth table of the expression A+B+C.D and that of the expression (A+B) + B.C + A.D + C.D are same A B C D CD A+B+CD

27. 13 24 13 24 13 24 57 68 13 24 75 86 15 26 913 1014 37 48 1115 1216 15 26 139 1410 48 37 1512 1611 (a) (b) (c) (d) (e)(f) (a) Box number of K-map corresponding to the two variable truth table; (b) Box number of K-map corresponding to the three variable truth table; (c) Box number of K-map corresponding to the four variable truth table; (d) Sequence number of K-map corresponding to the two variable truth table; (e) Sequence number of K-map corresponding to the three variable truth table; (f) Sequence number of K-map corresponding to the four variable truth table.

28. A BC AB 0 1 0101 00 01 11 10 0101 K-map of two-variable Truth table K-map of three-variable Truth table 0 1 1 1 1 1 0 0 0 1 0 1 3 2 4 1 3 7 5 2 4 8 6 (b) A B C D Y 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 1 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 Sequence 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A B C Y 0 0 0 1 0 0 1 0 0 1 0 1 1 0 1 0 0 0 1 0 1 1 0 1 1 1 Sequence 1 2 3 4 5 6 7 8 A B Y 0 0 0 0 1 1 1 0 1 1 1 1 Sequence 1 2 3 4 AB CD 00 01 11 10 00 01 11 10 K-map of four-variable Truth table 00100010 000 111 000 000 1 5 13 9 2 6 14 10 4 8 16 12 3 7 15 11 (a)(c) (d)(e) (f) Figure illustrates how K-map has been derived from the given two-, three-, and four-variable truth tables.

29. A B 0 1 0101 1 1 3 2 4 C AB 00 01 11 10 0101 0 1 1 0 0 0 1 0 1 3 7 5 2 4 8 6 AB CD 00 01 11 10 00 01 11 10 11111111 000 000 000 000 1 5 13 9 2 6 14 10 4 8 16 12 3 7 15 11 Pairs Quads C AB 00 01 11 10 0101 0 1 1 0 1 3 7 5 2 4 8 6 Quads C AB 00 01 11 10 0101 1 0 0 1 1 3 7 5 2 4 8 6 Quads C AB 00 01 11 10 0101 1 1 0 0 1 1 1 3 7 5 2 4 8 6 Quads AB CD 00 01 11 10 00 01 11 10 11101110 011 010 111 111 1 5 13 9 2 6 14 10 4 8 16 12 3 7 15 11 An octet A quad A pair (a)(b) (C) (d) (e) (f) (g) One of the step in the K- map procedure is to form groups of adjacent ‘1’s. Groups of 2, groups of 4, and groups of 8 could be formed. These groups are called pairs, quads, and octets, respectively, as shown in the figure. The presence of pairs, quads, and octets purely depends on the truth table at hand. The K-map uses some rules as far as grouping of adjacent boxes containing ‘1’s is concerned.

30. A B C D Y 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 Sequence 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AB CD 00 01 11 10 00 01 11 10 11111111 000 001 000 011 1 5 13 9 2 6 14 10 4 8 16 12 3 7 15 11 Boolean Expression Truth table (Given or derived from the Boolean Expression) Its K-Map An example of K-map based minimisation process. Consider a K-map, as shown in figure, which has been derived from a given truth table (also shown). There are three groups, one singular group (sequence number 4), a pair, and a quad.

31. A B C D ABAB Realisation of logic expression

32. Y = A + B ABAB OR Y = A.B ABAB +V AND +V CMOS NOT (a)(b)(c) The NOT gate and SR flip-flop illustrated earlier uses bipolar transistors. Such gates and logic circuits can also be designed even using diodes. Above figure shows the realization of a two-input AND gates, and a two-input OR gate using diodes. (c) shows CMOS logic of a NOT gate.

33. Location-0 Location-1 Location-2 Location-3 Location-4 Location-5 Location-6 Location-7 Location-8 Location-9 Location-10 Location-11 Location-12 Location-13 Location-14 Location-15 Least significant bit B-7 B-6 B-5 B-4 B-3 B-2 B—1 B-0 Most significant bit Semiconductor-based memory cells that are fabricated on a single piece of material (wafer) can accommodate a large number of data bytes. These are called memory ICs. Figure shows a schematic illustration of a semiconductor memory. The semiconductor memory has 16 locations, Location-0 to Location-15. Each location is a byte long containing, eight bits. The bit positions of each byte are defined by B 0 through B 7. B­ 0 is called the Least Significant Bit (LSB) and B 7 is called the Most Significant Bit (MSB).

34. Address linesData lines Chip enable Read/Write enableGround The above figure shows a schematic pin out diagram of a typical RAM chip. The chip is selected prior to a reads and writes operation. If it is a read operation the Read/Write signal is ‘low’ and if it is a write operation the Read/Write signal is ‘high.’ The chip must have an address lines in order to address the location in which the data is to be stored or from which the stored data is to be retrieved. The number of address lines solely depends on the number of locations the chip has.