1. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Victor Luyali C.E. Group Synopsys Optimization Results (II)

2. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Design Optimization Constraints Dynamic Power Dissipation : Capacitance, Frequency, Activity und Supply Voltage. Supply voltage unchangeable! Speed : τ = RC Speed : Critical Path, Gate Count Load Capacitance C L : Fanout

3. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Transition max_transition Fan Out max_fanout Capacitance max_capacitance, min_capacitance Timing Constraints: Clks,Delay and Frequency Optimization:Architectural,Logic gate Level Synopsys responds to the set Constraints accordingly.

4. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Commands Used -Desired Speed, Frequency set_max_frequency -Desired Area set_max_area -Desired Power set_max_dyn_power -Max Capacitance of between 0,04 and 0,03 used but eventually 0,04. -Fan out of between 2 and 4,but 2 and 3 resulted in various Violations.

5. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Freq (MHz) Max Delay ( ns) Max Area Dyn Power (uW) PDP 10001,041000000142,7775*148,4886 10001,041000000117,2635*129,9540 10001,08120000097,0772#*104,8434 10001,081000000121,9309#131,6854 9501,081000000121,3593*131,0680 9501,071000000121,4278*129,9277 9001,08900000121,3563#131,0648 9001,09800000121,0492131,9436 8001,091090000120,3473131,1786 10001,091090000122,0093132,9901 8001,091090000120,7934~131,6649 9001,091090000121,7751~*132,7349

6. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design -Violations during Optimization: # area, * fanout, ~ Slack -Caused by trial and error methods when setting constrainsts -It is expected : Low fanout,low power consumption but higher speed -Fan out increase – increase in Load capacitance hence increased dyn power consumption !Synopsys could resort to larger gates which may increase power consumption due to large input capacitances -Smaller area-smaller critical path which should reduce power Results/Analysis

7. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Conclusion The Results do not entirely correspond to the expected Pattern due to the prescence of Violations in Timing,Area,Capacitance and Fan out Constraints