1. T IMERS - 2

2. O UTPUT U NIT Each capture/compare block contains an output unit. The output unit is used to generate output signals such as PWM signals. Each output unit has eight operating modes that generate signals based on the EQU0 and EQUx signals. Output Modes

3. T IMER IN U P M ODE The OUTx signal is changed when the timer counts up to the TACCRx value, and rolls from TACCR0 to zero, depending on the output mode.

4. T IMER IN C ONTINUOUS M ODE Timer in Continuous Mode

5. O UTPUT U NIT The TACCTLn registers are cleared by a power-on reset (they are not affected by a power-up clear). Interrupts from Timer_A: Interrupts can be generated by the timer block itself (flag TAIFG) and each capture/compare channel (flag TACCRn CCIFG or CCIFGn for short). TACCR0 is privileged and has its own interrupt vector, TIMERA0_VECTOR. Its priority is higher than the other vector, TIMERA1_VECTOR, which is shared by the remaining capture/compare channels and the timer block.

6. M EASUREMENT IN THE C APTURE M ODE The Capture mode is used to take a time stamp of an event; to note the time at which it occurred. A measurement typically requires two or more captures. The timer can be used in two opposite ways, In most cases the timer clock is either ACLK or SMCLK, whose frequency is known, and the unknown signal is applied to the capture input. To measure the length of a single pulse, we should capture both edges and subtract the captured times. This gives the duration of the pulse in units of the timer clock’s period. For a periodic signal we might capture only the rising edges (or falling if preferred) and the difference gives the period directly. The period of the timer clock should be much less than the duration of the signal to give good resolution. The opposite approach is used to measure a signal with a high frequency. The signal is used as the timer clock and the captured events are typically edges of ACLK, whose frequency is known. The difference between that and the captured value gives the number of cycles of the signal in one cycle of ACLK. This gives the frequency rather than the period. The first method is much more common.

7. M EASUREMENT OF F REQUENCY : C OMPARISON OF SMCLK AND ACLK The general principle for measuring a frequency f is to count the number of cycles N in a known interval of time T, whence f = N/T. If T = 1s then N gives the frequency in hertz directly. Alternatively, if T = 1 ms then N gives the frequency in kilohertz. The signal under test is used as the timer clock and an external signal should be applied to the TACLK pin. Remember to set the PnSEL.x bit to connect this pin to the timer and select TACLK or INCLK using the TASSELx bits. The channel is configured to capture the value of TAR and request an interrupt at a rising edge of ACLK. This value N 1 is stored during the ISR. The next rising edge of ACLK stimulates another capture and interrupt. The difference between the new and old values of TAR, N 2 − N 1, gives the number of cycles of the test signal in one cycle of ACLK. Thus the measured frequency is f = (N 2 − N 1 )f ACLK.

8. O UTPUT IN THE C ONTINUOUS M ODE In the Continuous mode, TAR counts from 0 up to 0xFFFF and returns to 0 on the next clock transition, setting TAIFG as it does so. The only control over the period of TAR in real time is through the choice of clock, which is so coarse that it will rarely give the desired value. Therefore the duration of output signals must almost always be controlled by software rather than the period of the timer.

9. P ULSE -W IDTH M ODULATION Microcontrollers are often required to vary the power supplied to a load through a continuous range, not just on or off. This might seem to call for a digital-to-analog converter, or DAC, but very few microcontrollers contain true DACs. A few MSP430s provide them but most do not. The reason is that pulse-width modulation, or PWM, provides an adequate substitute for a DAC in most applications. It requires only a timer, which is purely digital and therefore much simpler and cheaper to fabricate than the analog circuits required for a DAC. The idea behind PWM is very simple: The load is switched on and off periodically so that the average voltage has the desired value. The fraction of the time while the load is active is called the duty cycle D. Assume that the output is driven either to ground or to V CC. Then the average voltage across the output is given by

10. PWM Edge-aligned pulse-width modulation

11. S IMPLE PWM The usual arrangement for PWM is that each output is turned on when TAR returns to 0 and turned off after a variable time that gives the desired duty cycle. This means that increasing the value in TACCRn increases the duty cycle, which makes the operation simpler to understand. This needs the Reset/Set output mode (7) for loads driven active high. This is sometimes called positive PWM. Conversely, the Set/Reset mode (3) should be used for active low loads or negative PWM. The duty cycle is given by

12. D ESIGN OF PWM There are two main parameters that must be chosen before suitable values can be selected for PWM: The number of desired values of the duty cycle (the resolution). The frequency of the output waveform. These are linked because it is not possible to have both high resolution and a high frequency. Suppose that the duty cycle of the output is specified in percent to the nearest integer. This means that there are 101 possible values of 0, 1, 2,..., 99, 100%. The simplest way of handling this is to choose TACCR0 = 99, which gives a period of 100 counts. The desired duty cycle in percent can then be written directly to TACCRn for channel n (where n > 0). Remember that the denominator for the duty cycle is (TACCR0+1).

13. D ESIGN OF PWM The appropriate frequency f PWM of the output waveform depends strongly on the type of load. Anything higher than about 100 Hz is sufficient for an LED. The period of the PWM is the same as that of the timer and the frequency is therefore given by This means that f timer clock must be above 100 Hz×100 counts = 10KHz for the LED. There would be no problem in running the timer fromACLK at 32 KHz except that 10 KHz is not readily available. The simple options are f ACLK / 2 = 16KHz or f ACLK / 4 = 8 KHz. It would be better to choose the higher frequency to avoid visible flashing of the LED.