1. 15-213 Recitation 7 Greg Reshko Office Hours: Wed 2:00-3:00PM March 31 st, 2003

2. Outline Virtual Memory  Paging  Page faults  TLB  Address translation Malloc Lab  Lots of hints and ideas

3. Virtual Memory Reasons  Use RAM as a cache for disk  Easier memory management  Protection  Enable ‘partial swapping’  Share memory efficiently

4. Physical memory CPU 0: 1: N-1: Memory Physical Addresses

5. Virtual Memory CPU 0: 1: N-1: Memory 0: 1: P-1: Page Table Disk Virtual Addresses Physical Addresses

6. Paging: Purpose Solves two problems  External memory fragmentation  Long delay to swap a whole process Divide memory more finely  Page – small logical memory region  Frame – small physical memory region Any page can map to any frame

7. Paging: Address Mapping Logical Address PageOffset.... f29 f34.... FrameOffset Page table Physical Address

8. Paging: Multi-Level P1Offset.... f29 f34 f25 FrameOffset Page Tables.... f99 f87.... P2.... f07 f08.... Page Directory

9. Page Faults Virtual address not in memory  This means it is on a disk  Go to disk, fetch the page, load it into memory, get back to the process CPU Memory Page Table Disk Virtual Addresses Physical Addresses CPU Memory Page Table Disk Virtual Addresses Physical Addresses

10. Copy-on-Write “Simulated” Copy  Copy page table entries to new process  Mark PTEs read-only in old and new What really happens  Process writes to page  Page fault handler is called Copy page into empty frame Mark read-write in both PTEs Result  Faster and less work

11. Relevance to Fork Why is paging good for fork and exec?  Fork produces two very similar processes Same code, data, and stack  Copying all pages is expensive Many will never be modified (especially in exec)  Share pages instead i.e. just mark them as read only and duplicate when necessary

12. Address Translation: General Idea Mapping between virtual and physical addresses Processor Hardware Addr Trans Mechanism fault handler Main Memory Secondary memory V P  page fault physical address OS performs this transfer (only if miss) virtual addresspart of the on-chip memory mgmt unit (MMU)

13. Address Translation: In terms of address itself Higher bits of the address get mapped from virtual address to physical. Lower bits (page offset) stays the same. virtual page numberpage offset virtual address physical page numberpage offset physical address 0p–1 address translation pm–1 n–1 0p–1p

14. TLB Translation Lookaside Buffer  Small hardware cache in MMU  Maps virtual page numbers to physical page numbers CPU TLB Lookup Cache Main Memory VAPA miss hit data Trans- lation hit miss

15. ... Address Translation with TLB virtual address virtual page number page offset physical address n–10p–1p validphysical page numbertag validtagdata = cache hit tagbyte offset index = TLB hit TLB Cache

16. Example Motivation:  A detailed example of end-to-end address translation  Same as in the book and lecture I just want to make sure it makes perfect sense  Do practice problems at home Ask questions if anything is unclear

17. Example: Description Memory is byte addressable Accesses are to 1-byte words Virtual addresses are 14 bits Physical addresses are 12 bits Page size is 64 bytes TLB is 4-way set associative with 16 total entries L1 d-cache is physically addressed and direct mapped, with 4-byte line size and 16 total sets

18. Example: Addresses 131211109876543210 11109876543210 VPO PPOPPN VPN (Virtual Page Number) (Virtual Page Offset) (Physical Page Number) (Physical Page Offset) 14-bit virtual addresses 12-bit physical address Page size = 64 bits

19. Example: Page Table VPNPPNValid 00281 01–0 02331 03021 04–0 05161 06–0 07–0 VPNPPNValid 08131 09171 0A091 0B–0 0C–0 0D2D1 0E111 0F0D1 …

20. Example: TLB 16 entries 4-way associative 131211109876543210 VPO VPN TLBI TLBT SetTagPPNValidTagPPNValidTagPPNValidTagPPNValid 003–0090D100–007021 1032D102–004–00A–0 202–008–006–003–0 307–0030D10A34102–0

21. Example: Cache 16 lines 4-byte line size Direct mapped 11109876543210 PPOPPN CO CI CT IndexTagValidB0B1B2B3IndexTagValidB0B1B2B3 01919911231182413A005189 1150––––92D0–––– 21B100020408A2D19315DA3B 3360––––B0B0–––– 4321436D8F09C120–––– 50D13672F01DD16104963415 6310––––E13183771BD3 716111C2DF03F140––––

22. Example: Address Translation Virtual Address 0x03D4 Split into offset and page number  0x03D4 = 00001111010100  VPO = 010100 = 0x14  VPN = 00001111 = 0x0F Lets see if this is in TLB  0x03D4 = 00001111010100  TLBI = 11 = 0x03  TLBT = 000011 = 0x03

23. Example: TLB 16 entries 4-way associative 131211109876543210 VPO VPN TLBI TLBT SetTagPPNValidTagPPNValidTagPPNValidTagPPNValid 003–0090D100–007021 1032D102–004–00A–0 202–008–006–003–0 307–0030D10A34102–0

24. Example: Address Translation Virtual Address 0x03D4 TLB lookup  This address is in TLB (second entry, set 0x3)  PPN = 0x0D = 001101  PPO = VPO = 0x14 = 010100  PA = PPN + PPO = 001101010100 Cache  PA = 0x354 = 0x001101010100  CT = 001101 = 0x0D  CI = 0101 = 0x05  CO = 00 = 0x0

25. Example: Cache 16 lines 4-byte line size Direct mapped 11109876543210 PPOPPN CO CI CT IndexTagValidB0B1B2B3IndexTagValidB0B1B2B3 01919911231182413A005189 1150––––92D0–––– 21B100020408A2D19315DA3B 3360––––B0B0–––– 4321436D8F09C120–––– 50D13672F01DD16104963415 6310––––E13183771BD3 716111C2DF03F140––––

26. Example: Address Translation Virtual Address 0x03D4 Cache Hit  Tag in set 0x5 matches CT  Data at offset CO is 0x36  Data returned to MMU  Data returned to CPU

27. Lab 6 Hints and Ideas Due April 16 40 points for performance 20 points for correctness 5 points for style Get the correctness points this week  Get a feel for how hard the lab is  You'll probably need the time  Starting a couple days before is a BAD idea!

28. How to get the correctness points We provide mm-helper.c which contains the code from the book  malloc works  free works (with coalescing)  Heap checking doesn't work  realloc doesn't work Implement a dumb version of realloc  malloc new block, memcpy, free old block, return new block

29. How to get the correctness points Implement heap checking  Have to add a request id field to each allocated block (tricky)  Hint: need padding to maintain 8 byte alignment of user pointer  In the book's code bp always the same as the user pointer The 4 bytes immediately before bp contain size of payload 3 lsb of size unused (because of alignment)  first bit indicates of the block is alloced or not Size+aPayload…Footer bp

30. How to get the correctness points Need to change block layout to look like this: This changes how the implicit list has to be traversed  But size is at same place relative to bp Size+aPayload…Footer bp ID

31. How to get the correctness points Or change block layout to look like this: All accesses to what was size now access id but can be clever and make size 4 bytes larger Could even make bp point to id.. Most code would just work IDPayload…Footer bp Size+a

32. How to get the correctness points Once malloc, free, and realloc work with the id field, write heapcheck  Iterate over the whole heap and print out allocated blocks  Need to read the id field… That's it for correctness

33. Hints Remember that pointer arithematic behaves differently depending on type of pointer Consider using structs/unions to eliminate some messy pointer code Get things working with the short trace file first:./mdriver -f short1-bal.rep To get the best performance  Red-Black trees  Ternary trees  Other interesting data structures

34. That’s it for hints… Good Luck!