1. CSE 567 - Autumn 1998 - Combinational Logic - 1 Multi-Level Optimization z1. Reduce number of literals yfewer literals means less transistors (less space) yfewer inputs implies faster gates (less switches in series) yfan-ins (# of gate inputs) are limited in some technologies z2. Reduce number of gates ynumber of gates (or gate packages) influences manufacturing costs z3. Reduce number of levels of gates yfewer levels of gates implies reduced signal propagation delays yminimum delay configuration typically requires more gates (wider less deep circuits) zExplore tradeoffs between increased circuit delay and reduced gate count yautomated tools to optimize logic and explore possibilities

2. CSE 567 - Autumn 1998 - Combinational Logic - 2 X = AC'D + BC'D + ACD' + BCD' (12 literals and 4 wires, max fan-in = 4) X = (A+B)C'D + (A+B)CD' (8 literals and 6 wires, max fan-in = 2) X = (A+B)(C xor D) (4 literals and 2 wires, max fan-in = 2) Optimization Approaches zExploit common subexpressions (less gates) zMinimize number of literals rather than terms zTrade more levels of logic for reduced fan-in (may also be faster) zNo systematic minimization procedure exists as in the two-level case

3. CSE 567 - Autumn 1998 - Combinational Logic - 3 manipulate network via a collection of transformations there exists no algorithm that guarantees an "optimal" multi-level network will be obtained inputs outputs each node is an arbitrarily complex gate Network Operations zOperations on factored forms yelimination ydecomposition yextraction ysimplification ysubstitution

4. CSE 567 - Autumn 1998 - Combinational Logic - 4 divisor quotient remainder interesting divisors are called kernels and cubes Factoring Boolean Expressions zDivision with Boolean functions F = DQ + RD = divisor Q = quotient R = remainder zExample: X = ac + ad + bc + bd + e Y = a + b X/Y = c + dX = Y (c + d) + e

5. CSE 567 - Autumn 1998 - Combinational Logic - 5 G does not divide F under algebraic rules G does divide F under Boolean rules (very large number of these) the key here is the absorption theorem of Boolean algebra Algebraic vs. Boolean Division zAlgebraic division – use rules of algebra (see previous example) zBoolean division – use rules of Boolean algebra F = ad + bcd + e G = a + b F/G = (a + c) d F = GQ + R =[G (a + c) d] + e (a + b) (a + c) d + e (aa + ac + ab + bc) d + e (a + bc) d + e ad + bcd + e

6. CSE 567 - Autumn 1998 - Combinational Logic - 6 Kernels and Cubes zKernel: cube-free factor of an expression (no cube can factor it evenly) kernels:a + b, a + cd non-kernels:a, abc, a(c + d) zCo-kernel: quotient resulting from dividing the expression by the kernel e.g., F = a c + b c + b’ d’kernels:a + b co-kernels: c G = (a + b + c) (d + e) f + gkernels:a + b + c; d + e co-kernels: de, df; af, bf, cf

7. CSE 567 - Autumn 1998 - Combinational Logic - 7 Why Kernels? zMulti-cube algebraic divisors (only other divisors are cubes) zCan be partitioned into a hierarchy (efficient extraction algorithms) ylevel-0 kernel: cannot be divided evenly by a kernel ylevel-n kernel: can be divided evenly only by level-(n-1) kernels and itself F = (a (b + c) + d) (eg’ + g (f + e’)) + (b + c) (h + i) level-0 (among others):b + c level-1 (among others):a (b + c) + d level-2:F F = j (a (b + c) + d) (eg’ + g (f + e’)) + (b + c) (h + i) F is level-3 because it contains a level-2 kernel: (a (b + c) + d) (eg' + g (f + e'))

8. CSE 567 - Autumn 1998 - Combinational Logic - 8 Tabular Method for Finding Kernels zUse a cube-literal matrix zRectangles represent a cube zThe co-rectangle represents a kernel ze.g. g = abe + acd + bcd zcube = cd zkernel = a+b

9. CSE 567 - Autumn 1998 - Combinational Logic - 9 Common-Cube Extraction zFind the cubes common two several expressions zUseful for extracting the cubes (factoring) ze.g. F = abc + abd +eg G = abfg H = bd + ef

10. CSE 567 - Autumn 1998 - Combinational Logic - 10 Finding Kernel Intersectons zFirst find the kernels and co-kernels (cubes) ze.g.F = af + bf + ag + cg + ade + bde + cde G = af + bf + ace + bce H = ade + cde z(Number these cubes in order of appearance)

11. CSE 567 - Autumn 1998 - Combinational Logic - 11 Finding Kernel Intersections zThe cokernel-cube matrix zA column for each cube zA row for each cube in each function zNumbers indicate which cubes in the corresponding kernel zRectangles in this matrix correspond to common kernels

12. CSE 567 - Autumn 1998 - Combinational Logic - 12 abcdeabcde wxyzwxyz p = ce + de v = a’d + bd + c’d + ae’ s = r + b’ t = ac + ad + bc + bd + e u = q’c + qc’ + qcq = a + b r = p + a’ Example to Illustrate Transformations zUnoptimized logic network

13. CSE 567 - Autumn 1998 - Combinational Logic - 13 j = a’ + b + c’v = jd + ae’ s = ke + a’ + b’ t = kq + e u = q + c k = c + d abcdeabcde wxyzwxyz q = a + b Example to Illustrate Transformations (cont’d) zOptimized network

14. CSE 567 - Autumn 1998 - Combinational Logic - 14 abcdeabcde wxyzwxyz p = ce + de v = a’d + bd + c’d + ae’ s = p + a’ + b’ t = ac + ad + bc + bd + e u = q’c + qc’ + qcq = a + b Elimination zRemoving a node (too simple a function, better to absorb into other gates)

15. CSE 567 - Autumn 1998 - Combinational Logic - 15 abcdeabcde wxyzwxyz p = ce + de v = jd + ae’ s = r + b’ t = ac + ad + bc + bd + e u = q’c + qc’ + qcq = a + b r = p + a’ j = a’ + b + c’ Decomposition zBreak a complex node into simpler ones (too complex for a single gate, create opportunities for sharing sub-expressions)

16. CSE 567 - Autumn 1998 - Combinational Logic - 16 abcdeabcde wxyzwxyz p = ke v = a’d + bd + c’d + ae’ s = r + b’ t = ka + kb + e u = q’c + qc’ + qcq = a + b r = p + a’ k = c + d Extraction zFinding common sub-expressions and pulling them out into their own node (most important and complex function in multi-level optimization)

17. CSE 567 - Autumn 1998 - Combinational Logic - 17 abcdeabcde wxyzwxyz p = ce + de v = a’d + bd + c’d + ae’ s = r + b’ t = ac + ad + bc + bd + e u = q + cq = a + b r = p + a’ Simplification zTwo-level minimization applied to a node (exploit structural don't cares)

18. CSE 567 - Autumn 1998 - Combinational Logic - 18 abcdeabcde wxyzwxyz p = ke v = a’d + bd + c’d + ae’ s = r + b’ t = kq + e u = q’c + qc’ + qcq = a + b r = p + a’ k = c + d Substitution zReuse existing nodes to make others simpler (closely linked to extraction and decomposition)

19. CSE 567 - Autumn 1998 - Combinational Logic - 19 a b x a =1, b = 1, x =1 can never occur Multi-Level Logic Don’t Cares zDon't cares come from two sources in multi-level circuits zFrom specification (external explicit don't cares) yin terms of circuit inputs and outputs zFrom structure of circuit graph (internal implicit don't cares) ya combination of input and internal values cannot occur or yan internal node output is irrelevant for some input combinations depending on how it is used by its fanout zBoth are critical in arriving at minimal circuits zMust be maintained throughout all graph operations

20. CSE 567 - Autumn 1998 - Combinational Logic - 20 A is a late arriving input that is moved closer to the output by restructuring the logic (i.e., changing DAG structure) AA Restructuring Multi-Level Logic for Speed zDecrease fanout of nodes ymore destinations for a signal implies slower transmission yelimination zDecrease fanin of nodes ygate speed proportional to square of number of inputs (1st order) ydecomposition, simplification zMove late input closer to outputs ymake path to output shorter, pre-compute other logic yShannon decomposition (f = a f a + a’ f a’ )

21. CSE 567 - Autumn 1998 - Combinational Logic - 21 Summary of Multi-Level Optimization zMinimization procedures yheuristic application of the operations we just listed yno guarantee of finding an optimal realization ydoes quite well in a practical amount of time (with algebraic division) zEverything up to this point has been technology independent yjust considering literal count or depth of circuit ynot the types of elements available to actually implement the circuit zTechnology mapping yprocess of converting circuit graph into one where each node is directly implementable with an available gate or function block

22. CSE 567 - Autumn 1998 - Combinational Logic - 22 NAND2 area: 4 delay: 2 NAND4 area: 8 delay: 8 AOI21 area: 6 delay: 5 XOR2 area: 16 delay: 6 Technology Mapping zProcess of transforming logic network so that all nodes can be directly implemented with an available component directed toward area or speed optimization zRequires library of available gates ypermutations of inputs (e.g., ab + c – a and b can be switched) yarea and delay for each library gate zExample:

23. CSE 567 - Autumn 1998 - Combinational Logic - 23 Canonical Representation for Library Cells zRepresent function in terms of 2-input NAND gates zNot a unique representation ylibrary must represent all non-isomorphic possibilities zExample: yF = (ABCD)'has two representations

24. CSE 567 - Autumn 1998 - Combinational Logic - 24 node in graph cell in library     Technology Mapping by Tree Matching zDynamic programming algorithm ytaken from code generation – Aho and Johnson's TWIG zDAG is viewed as a forest of trees (two options) y1. partition into trees (break graph at fanout nodes) y2. duplicate logic in common sub-trees zConsider adding inverter pairs along any arc of original DAG