1. 2012 H4IRRAD test campaigns Summary of results S. Uznanski CERN, Geneva, Switzerland Radiation Working Group meeting Oct 16, 2012

2. S. Uznanski, RadWG Oct 16, 2012 2012 H4IRRAD test campaigns 2 3 H4IRRAD slots have been defined in 2012  1 st slot – May 15, 2012 – June 3, 2012  MAX5541 – 16-bit DAC  ADS1281 – Delta-Sigma ADC  DS18B20 – 1-wire thermometer  DS2401 – 1-wire ID  SPLargeUHD9 – 130nm SP SRAM  2 nd slot – Aug 03, 2012 – Aug 17, 2012  MAX5541 – 16-bit DAC  MIC37302 – Voltage regulator  3 rd slot – Nov 15, 2012 – Dac 3, 2012  MIC37302 – Voltage regulator  FGClite proto

3. S. Uznanski, RadWG Oct 16, 2012 2012 H4IRRAD test campaigns 3 3 H4IRRAD slots have been defined in 2012  1 st slot – May 15, 2012 – June 3, 2012  DS18B20 – 1-wire thermometer  DS2401 – 1-wire ID  MAX5541 – 16-bit DAC  ADS1281 – Delta-Sigma ADC  SPLargeUHD9 – 130nm SP SRAM  2 nd slot – Aug 03, 2012 – Aug 17, 2012  MAX5541 – 16-bit DAC  MIC37302 – Voltage regulator  3 rd slot – Nov 15, 2012 – Dac 3, 2012  MIC37302 – Voltage regulator  FGClite proto

4. S. Uznanski, RadWG Oct 16, 2012 DS18B20/DS2401 (1/3) 4 DUT description: Tester architecture and test procedure: DUT nameDUT typeTest typeSamples tested PackageDate codeLot code DS18B201-wire thermometer SEE, TID2 x 25TO-92unknown DS24011-wire IDSEE, TID2 x 25SOT-2239931C2DM914705AIB

5. S. Uznanski, RadWG Oct 16, 2012 DS18B20/DS2401 (2/3) 5 Beam conditions: SEE test results: Run Run start date Run end date Dose in Gy ± 50% HEH per cm2 ± 50% 1 Si MeV Neq ± 50% thermal neutrons ± x2 1 May 15, 2012 @ 3:05pm May 22, 2012 @ 12:30pm 4.5E+018.1E+103.3E+113.8E+10 2 May 22, 2012 @ 02:07pm May 25, 2012 @02:11pm 1.8E+013.3E+101.3E+111.5E+10 3 May 25, 2012 @ 02:11pm Jun 04, 2012 @09:41am 8.1E+011.5E+115.9E+116.9E+10 Run Run start date Run end date Iterations S/N ID err S/N comm err Th ID err Th Comm Err Th temp err 1 May 15, 2012 @ 3:05pm May 22, 2012 @ 12:30pm 1921700096 2 May 22, 2012 @ 02:07pm May 25, 2012 @02:11pm 762100021 3 May 25, 2012 @02:11pm Jun 04, 2012 @09:41am 27229000876

6. S. Uznanski, RadWG Oct 16, 2012 DS18B20/DS2401 (3/3) 6 Temperature drift: Conclusions: Temperature measurement drift observed during the slot is equal to 3.3e-2 ±1.2°C/Gy Component Dose (Gy) ±50% S/N ID err (cm2/HEH) S/N comm err (cm2/HEH) Th ID err (cm2/HEH) Th Comm Err (cm2/HEH) Th temp err (cm2/HEH) S/N (DS2401)143<4.4E-12 Xxx Th (18B20)143xx<4.4E-125.6E-109.2E-11

7. S. Uznanski, RadWG Oct 16, 2012 MAX5541 (1/2) 7 DUT description: Tester architecture and test procedure: DUT name DUT typeTest Type Samples tested Packag e Date codeLot code MAX554116-bit DACTID, SEE 3DIP/SOunknown

8. S. Uznanski, RadWG Oct 16, 2012 MAX5541 (2/2) 8 Beam conditions: Results:  Components have been irradiated up to 135, 123 and 118 Gy, no power consumption increase after irradiation, all components fully functional  No SEL have been detected  No SEFI/SETs have been observed during the slot SEL XS upper level < 3.80e-12 SEU/SEFI XS upper level < 3.80e-12 DUT num Test start date Test end date Dose in Gy ± 50% HEH per cm2 ± 50% 1 Si MeV Neq ± 50% thermal neutrons ± x2 1 15/05/2012 12:01 04/06/2012 16:56 1.35E+022.14E+118.61E+111.18E+11 2 15/05/2012 12:01 04/06/2012 16:56 1.23E+022.02E+118.54E+111.16E+11 3 15/05/2012 12:01 04/06/2012 16:56 1.18E+021.90E+118.18E+111.12E+11

9. S. Uznanski, RadWG Oct 16, 2012 ADS1281 (1/2) 9 DUT description: Tester architecture and test procedure: DUT name DUT typeTest Type Samples tested Packag e Date codeLot code ADS1281High-Res ADC TID, SEE 3TSSOP- 24 unknown

10. S. Uznanski, RadWG Oct 16, 2012 ADS1281 (2/2) 10 Beam conditions: Results:  Components have been irradiated up to 164, 132 and 128 Gy  No SEL have been detected: SEL XS upper level < 8.06E-13  No SEFI/SETs have been observed during the slot SEFI XS upper level < 8.06E-13 SEU on M0 upper level < 1.31E-12 SEU on M1 upper level < 1.53E-12  No significant power consumption increase have been observed DUT num Test start date Test end date Dose in Gy ± 50% HEH per cm2 ± 50% 1 Si MeV Neq ± 50% thermal neutrons ± x2 1 15/05/2012 12:01 04/06/2012 16:56 1.28E+022.50E+111.00E+121.24E+11 2 15/05/2012 12:01 04/06/2012 16:56 1.64E+022.34E+119.49E+111.19E+11 3 15/05/2012 12:01 04/06/2012 16:56 1.32E+022.21E+119.05E+111.23E+11

11. S. Uznanski, RadWG Oct 16, 2012 SPLargeUHD9 (1/2) 11 DUT description: Tester architecture and test procedure: DUT nameDUT typeTest Type Samples tested PackageSRAM generator version Lot code SPLargeUHD chip 1 CMOS SRAM TID, SEE1 x 4MbitPBGA 256+16 6.1.1@20021219.0unknown SPLargeUHD chip 2 CMOS SRAM TID, SEE1 x 4MbitPBGA 256+16 6.1.1@20021219.0unknown

12. S. Uznanski, RadWG Oct 16, 2012 SPLargeUHD9 (2/2) 12 Beam conditions: SEE test results: Test start date Test end date Dose in Gy ± 50% HEH per cm2 ± 50% 1 Si MeV Neq ± 50% thermal neutrons ± x2 15/05/2012 15:00 22/05/2012, 14:54:45 5.2E+019.2E+103.0E+114.0E+10 23/05/2012, 10:42:30 25/05/2012, 14:07:52 2.1E+013.7E+101.2E+111.6E+10 25/05/2012, 15:52:16 04/06/2012, 09:02:25 9.4E+011.7E+115.4E+117.2E+10 15/05/2012 15:00 04/06/2012, 09:02:25 1.6E+023.0E+119.6E+111.3E+11 Run#SEU #MBU (2) Events Chip1 Events Chip2 SEU XS (cm2/bit) MBU XS (cm2/bit) Total XS (cm2/bit) 1 (0xAA/0x55) 5308419324716283686.9E-147.7E-176.9E-14 2 (0x00/0xFF) 1864514628579100666.0E-141.5E-156.3E-14 3 (0x00/0xFF) 86000711839547464536.1E-141.6E-156.5E-14 ‘A’/‘5’ ‘0’/‘1’

13. S. Uznanski, RadWG Oct 16, 2012 2012 H4IRRAD test campaigns 13 3 H4IRRAD slots have been defined in 2012  1 st slot – May 15, 2012 – June 3, 2012  DS18B20 – 1-wire thermometer  DS2401 – 1-wire ID  MAX5541 – 16-bit DAC  ADS1281 – Delta-Sigma ADC  SPLargeUHD9 – 130nm SP SRAM  2 nd slot – Aug 03, 2012 – Aug 17, 2012  MAX5541 – 16-bit DAC  MIC37302 – Voltage regulator  3 rd slot – Nov 15, 2012 – Dac 3, 2012  MIC37302 – Voltage regulator  FGClite proto Not performed

14. S. Uznanski, RadWG Oct 16, 2012 2012 H4IRRAD test campaigns 14 3 H4IRRAD slots have been defined in 2012  1 st slot – May 15, 2012 – June 3, 2012  DS18B20 – 1-wire thermometer  DS2401 – 1-wire ID  MAX5541 – 16-bit DAC  ADS1281 – Delta-Sigma ADC  SPLargeUHD9 – 130nm SP SRAM  2 nd slot – Aug 03, 2012 – Aug 17, 2012  MAX5541 – 16-bit DAC  MIC37302 – Voltage regulator  3 rd slot – Nov 15, 2012 – Dac 3, 2012  MIC37302 – Voltage regulator  FGClite proto

15. S. Uznanski, RadWG Oct 16, 2012 FGClite proto (1/1) 15 DUT description: Results:  First FGClite mixed-field validation: Analog card, Network card and Simplified main board  GW will send the voltage reference and will read back the measurements on 3 channels  This test will allow us to:  Compute the SEL XS thanks to power monitoring and power cycling feature  Compute the SEFI/SEU XS of analog measurements