1. General Purpose FIFO on Virtex-6 FPGA ML605 board Students: Oleg Korenev Eugene Reznik Supervisor: Rolf Hilgendorf 1 Semester: spring 2012

2. Content 1.Project overview 2.Goals 3.Motivation 4.Specifications 5.Block Diagram 6.Initial steps 7.Possible solutions 8.Workflow 9.Timeline 2

3. Project Overview Design and implementation of General Purpose FIFO which allows usage of external memory(DDR III) as FIFO storage on Xilinx FPGA device Design and implement generic IP core of FIFO Design and implement GUI generator of IP core on PC Create design which serves as sample application 3

4. Our goals Gain experience in hardware development (VHDL environment) Explore and expertise FPGA work environment Create design with configurable word size FIFO size bandwidth Achieve best performance Minimize usage of FPGA resources Make our world a better place 4

5. Motivation Why do we need big FIFO? FPGA works relatively fast comparing to data transmission rate. So we need special storage to accumulate pre-processed and processed data. Xilinx provides us with standard and relatively small FIFO (cores). In case we need to process big chunks of data we will have to use big storage (FIFO). For example in signal processing. 5

6. Specifications Hardware Xilinx Virtex-6 ML605 FPGA Evaluation Kit DDR III memory Ethernet interface UART interface PC with Ethernet interface Software ISE Design Suite Logic Edition Version 13.2 PlanAhead Design and Analysis Tool ISIM/Modelsim 6

7. Virtex 6 FIFO User Logic on FPGA Host connection: ETHERNET/UART/PCIe Block Diagram 7 User Logic FIFO regionHost FIFO region AXI bus Memory Arbiter Host FIFO controllerUser Logic FIFO controller Host PC FIFO IN FIFO OUT FIFO IN CONTROLLER User Logic FIFO area Memory Controller

8. Initial steps External interface Define FIFO interface Define word size limitation and its connection to bandwidth Choose external memory interface Choose host data exchanging interface Internal architecture Define memory arbiter functionality Define main controller functionality Define host and user logic FIFO controllers functionality 8

9. Possible solutions Choose data exchanging interface Ethernet UART PCIe Choose external memory interface AXI interface Native interface User interface Max word size 128 bits Greater than 128 bits 9

10. Workflow Studying memory controller Studying usage of Ethernet for communication with PC Studying and generating standard FIFO with internal RAM Implementation generalized FIFO controller Implementing User Logic controller Implementing Host FIFO controller Implementing memory arbiter Implementing main FIFO controller Verification of design Implementing GUI for generating FIFO IP core Implementing sample design 10

11. Timeline 11 12/55/528/4DurationTask 1 week Studying to integrating and interfacing with memory controller 1 week Studying to integrate internal FIFO and defining User Logic FIFO interface 1 weekStudying communication with PC through Ethernet 1 weekMidterm Presentation