1. HARDWARE OPAL-RT MARC PASTOR Real-Time 2009 Montreal, Quebec, Canada

2. 2 CABINET TO CHASSIS WANDA4_TARGET WANDA4_EXPANSION PATCH_PANEL WANDA3 THIRD PARTY MODULE: UPS, POWER_BAR,ETHERNET_HUB,…..

3. 3 CABINET 19”:up to 49U high, up to 36” depth hardware accessories: slides, door, roll,… CHASSIS 19” THIRD PARTY:UPS (90v to 240v) Power Supply (AC-DC, DC-DC), Switching, Linear Power Bar, Ethernet Hub CHASSIS 19” OPAL: HIL 4U(PC + 6 slots), IO at the front WANDA4_TARGET 4U(PC + 4 slots), IO at the back WANDA4_EXPANSION 4U(4 slots + 4 slots), IO at the back WANDA3 3U(PC + 4 slots), IO at the back TEST DRIVE 9U(PC + 11 slots), IO at the back ML506 2UVirtex5 Stand-Alone Chassis ML506 4UVirtex5 in a WANDA4 PATCH PANEL 3U48 Analog or 32 Analog&32 Digital (monitoring, break, signal injection) MAPPING BOX 4UWire interconnection CONDITIONING BOX 4Ucontains Power and conditioning Boards MAPPING PANELS 4UTwisted pair Flat Cable Interconnection CABINET & CHASSIS

4. 4 CHASSIS TO BOARDS 1 ANALOG CONDITIONING BOARDS OP5220 OP5330 OP5340 OP5330 OP5222 OP5242 OP5222 OP5241

5. 5 CHASSIS TO BOARDS 2 DIGITAL CONDITIONING BOARDS OP5210 OP5311 OP5312 OP5231 OP5237 OP5238 OP5236

6. 6 BOARDS TO SIGNALS 1 To be released soon OP5311 OP5237 OP5236-1 OP5236-2 OP5231

7. 7 BOARDS TO SIGNALS 2 To be released soon OP5312 OP5237-1 OP5237-2 OP5236-1 OP5236-2 OP5238 OP5231

8. 8 BOARDS TO SIGNALS 3 OP5320 OP5330 OP5242 OP5241

9. 9 PATCH PANEL FRONT 16 CHANNELS DIN96 DB25 BREAKING FEATURE MONITORING FEATURE PATCHING FEATURE INSERTING FEATURE

10. 10 VERIFICATION OF SIMULATOR INPUTS AND USER OUTPUTS PATCH PANEL DEBUGGING TOOL 1

11. 11 VERIFICATION OF SIMULATOR OUTPUTS AND USER INPUTS PATCH PANEL DEBUGGING TOOL 2

12. 12 PATCH PANEL DEBUGGING TOOL 3 SIMULATOR INPUT/OUTPUT FRONT LOOP-BACK

13. 13 TARGET ARCHITECTURE (ACTUAL) 2.5GHZ,1333MHZ FSB,12MB cache 4 GB memory

14. 14 TARGET ARCHITECTURE (1Q 2010) 8 FLAT CABLES 40 PIN TO BE REPLACED WITH 2 PCIe CABLES

15. 15 FPGA OPAL FAMILY

16. 16 FPGA COMPARISON

17. 17 FPGA SPARTAN3-5M

18. 18 SPARTAN-2 VERSUS SPARTAN-3 RESOURCE ALLOCATION

19. 19 FPGA VIRTEX5 BLOC DIAGRAM VIRTEX5 SX50T PCIe X1 CABLE (1 to 2 meters) TWO WAYS TO DOWNLOAD A BITSTREAM: 1. Through Local JTAG port 2. Through PCIe X1 port PCIe X1 PORT 22 x DIGITAL CHANNELS: 22 Din or 22 Dout or 11 Din/11Dout 32 x ANALOG CHANNELS: 32 Ain or 32 Aout or 16 Ain/16Aout BIRECTIONAL BUFFERS MEZZANINE ADC or DAC MEZZANINE ADC or DAC CARRIER OPAL INTERFACE JTAG PORT LCD DISPLAY DIO BITSTREAM GENERATOR COMPUTER PCIe SLOT COMPUTER INTEGRATED FPGA DEVELOPMENT SYSTEM BLOC DIAGRAM 48 x DIGITAL CHANNELS: 48 Din or 48 Dout or 24 Din/24 Dout

20. 20 INTEGRATED FPGA DEVELOPMENT SYSTEM (VIRTEX5) FPGA VIRTEX5_PRODUCT 22 DIO 24 DIO-C 24 DIO-D 16 ANALOG-B 16 ANALOG-A ANALOG- MEZZANINE-A ANALOG- MEZZANINE-B JTAG PORT PCIe PORT PCIe CABLE ML506 BOARD

21. 21 Din & Dout CONFIGURATION For HARDWARE-IN-THE-LOOP, Din & Dout have to match the various types of USER interfaces. Actual Din & Dout cover the great majority of application. OPAL will comply with the new USER needs. Some of designed CUSTOMIZED PROTOTYPES for new application : 1. Digital Output differential (5 to 30 V) 2. Digital Input Common Cathode (5 to 30V) 3. Digital Level Shifter (from Unipolar to Bipolar Voltage) 4. Transceivers 4-20 mA 5. ……….. THE FOLLOWING SLIDES SHOW THE STANDARD AVAILABLE Din & Dout CONFIGURATION

22. 22 Dout_PULL_N-MOS OP5237-1

23. 23 Dout_PUSH_P-MOS OP5237-2

24. 24 Dout_PULL_TRANSISTOR OP5312

25. 25 Dout_PUSH-PULL OP6227

26. 26 Din_PULL_DIODE OP5311

27. 27 Din_CONSTANT_CURRENT OP5237-1 OP5237-2

28. 28 CUSTOMIZED HARDWARE INTERFACE USER REQUIREMENT OPAL SOLUTION USER CIRCUIT BUILT ON PROTOTYPE BOARDS

29. 29 NEW CHASSIS DEVELOPMENT_TOP TYPICAL EXEMPLE WE USE 2 EXTERNAL MECHANICAL CONSULTANTS

30. 30 NEW CHASSIS DEVELOPMENT_BOTTOM TYPICAL EXEMPLE

31. 31 Visit & Contact Us For more information on Opal-RT’s complete line of Real-Time Simulators, HIL Testing and Rapid Control Prototyping products, please visit: