1. Chipset Basic One fact about computer system is that Microprocessor is always faster than peripheral devices to which it must communicate, this fact has forced to develop control chips which are used to control communication between the slower devices and CPU. In early PCs it was common to have separate chips for different purpose, and here the disadvantage – separate chips require more space on motherboard. Early computers have following different chips for different purpose(in addition to microprocessor chip) 1.Clock generator – 8284 2.Bus controller – 8288 3.System timer – 8253 4.Interrupt controller – 8259 5.DMA controller – 8237 6.Keyboard controller - 8255

2. So to overcome more space requirement for different chips first time in 1986 a company called Chips and Technologies introduced a revolutionary component 82C206, a integrated chip which contain the functionality of 8288,8284,8237 and 8259. In such a way a chipset (set of different chips ) concept introduced in computer industry. “chipset technically a group of chips that helps the processor to communicate and control different devices plugged into the motherboard” Advantages of chipset It made designing a motherboard much easier. Reduce the cost of motherboards. Chipset reduce the size of motherboard which is very much suitable for Personal Computers.

3. Architecture of chipset There are two types chipset architecture 1.North – South bridge architecture 2.Hub architecture Before going to chipset architecture remember one fact that chipset designing is depend on designs of processor, memory and BIOS.

4. North – South bridge architecture Connected through PCI bus (speed 33MHz)

5. It is a two chip architecture one chip is called as NORTH BRIDGE and other is SOUTH BRIDGE. Some early Intel chipset and all non-Intel chipsets are based on this architecture. NORTH BRIDGE : North bridge is a circuitry that provide support and control for the main memory, cache memory of CPU, clock generator and AGP (accelerated graphics port) interface as shown in above figure. It is a connection between high speed processor bus and low speed AGP and PCI buses. North bridge circuitry also known as PAC(PCI/AGP Controller). North bridge is the only circuitry on motherboard beside processor that runs at full motherboard speed(processor speed).

6. SOUTH BRIDGE South bridge include controllers for peripheral devices,the serial port and any other controller not essential for basic functioning of computer. It is a connection between the PCI bus and ISA bus,IDE bus, USB bus. South bridge chip is a lower speed chip and identical for each and every chipset design even for different manufacturers.

7. Hub architecture Microprocessor MEMORYMEMORY Memory Controller Hub I/O Controller Hub AGPAGP MEMORYMEMORY PCI expansion slot USB controller serial and parallel port Floppy & IDE controller Connected through HUB interface (speed 66MHz)

8. Introduction to Hub Architecture The newer 800 series chips use hub architecture instead of North-South bridge, in which north bridge chip is now called Memory Controller Hub(MCH) and south bridge is called as I/O Controller Hub(ICH) Rather than connect MCH and ICH through PCI bus as in standard North-South bridge, they are connected through dedicated hub interface which is twice faster than PCI bus.

9. Advantages of HUB architecture over North-South bridge architecture 1) Hub interface is faster : the hub interface is 4x(quad coupled),66MHz and 8bit interface means 4 * 66 MHz * 1byte = 266MBps Which has twice the throughput of PCI (33MHz * 32bit = 133MBps) 2) Reduced PCI loading : Hub interface is independent of PCI and doesn’t steal or share bandwidth for chipset. This improves performance of other PCI connected devices. 3) Reduced board wiring Although twice as fast as PCI, hub interface is only 8bit wide and require only 15 signals to be routed on the motherboard, by comparison PCI requires 64 signals which require more wires on motherboard.

10. Intel 915g chip set architecture Intel Pentium 4 Intel GMA 900 Graphics PCI Express X16 Graphics Intel High definition audio 4 PCI Express X1 8 High Speed USB 2.0 ports 6 PCI DDR/DDR2 82915g GMCH ICH6R BIOS Intel Matrix Storage Technology 4 SATA ports 6.4GB/s DMI 2GB/s 60 MB/s 500 MB/s 8 GB/s 150 MB/s 133 MB/s 8.5GB/s

11. Features of Intel 915g chipset Support 800Mhz and 533Mhz system bus,which is used to connect the microprocessor. So we can attach 800MHz and 533Mhz processor. Support for hyperthreading concept of Pentium 4 processor. To interlink GMCH and ICH a special Direct Media Interface (DMI) is used which can deliver data up to 2GB/s while previous Hub interface provide the bandwidth up to 266MBps. Intel 915g chipset come with PCI Express X1 and X16 technology provide data transfer rate 500MBps and 8GBps respectively. To support backward compatibility 6 PCI slots available of speed 133MBps. Intel 915g chipset support DDR/DDR 2 RAM slots with speed 8.5GBps.

12. It can support 8 ports of high speed USB 2.0 interface(60MBps) It support matrix storage technology that is the RAID concept to protect the digital memories. 4 SATA type connectors available. Support new audio formats such as Dolby Digital.

13. Intel 945g chipset architecture Intel Pentium D 533/800/1066MHz Intel GMA 900 Graphics PCI Express X16 Graphics Intel High definition audio 4 PCI Express X1 8 High Speed USB 2.0 ports 6 PCI DDR2 82945g GMCH ICH7R BIOS Intel Matrix Storage Technology 4 SATA ports 8.5GB/s DMI 2GB/s 60 MB/s 500 MB/s 8 GB/s 3gb MB/s 133 MB/s 10.7GB/s Media Expansion Card

14. Features Support for Pentium D processor up to 1066MHz bandwidth. Support for Active management technology: hardware-based technology for remotely managing and securing PCs. DDR2 dual channel system memory support with speed 10.7GBps. Also add the features of Intel 915g chipset.

15. ISA (Industry Standard Architecture) ISA bus architecture introduced first in IBM PC in 1981. ISA bus architecture is now obsolete(not used). ISA slots on mother board come in black color. There are two type of ISA bus 8 bit ISA 16 bit ISA 8 bit ISA 62 pins 8 data lines 20 address lines 6 interrupt request pins 3 DMA pins Operate with bandwidth 4.77MHz. (speed up to 5MBps)

16. 16 bit ISA 98 pins 16 data lines 20 address lines 11 interrupt request pins 7 DMA pins Operate with bandwidth 8MHz. (speed up to 10MBps)

17. Peripheral Component Interconnect (PCI) Features of PCI Expansion bus Wider data path PCI expansion bus come with 32bit and 64bit data path. 32 bit PCI bus can be used with 32bit microprocessors(eg. 80486) but these 32bit expansion slots are become less effective when new 64bit microprocessors are introduced, to overcome this problem wider data path 64bit PCI buses introduced.

18. High Speed 32bit and 64bit PCI bus with 33MHz bandwidth can support 133MBps and 266MBps data transfer rate respectively. A 64bit PCI with 66MHz bandwidth can support 524MBps data transfer rate. Backward Compatibility It is possible to design a new PCI bus on motherboard which already have ISA slots because of this we can design a motherboard with older ISA as well as new PCI. (no need to remove older ISA slots from motherboard to use PCI).

19. Bus Mastering Motherboards with PCI bus can do bus master transfer allowing them to bypass the CPU and RAM when transferring data between different peripherals.

20. Support to plug and play PCI support the PnP standard developed by hardware vendors in 1992. Just insert the PCI board in to the motherboard & turn the system ON, system automatically configure the PCI board & assign address to it.

21. TYPES OF RAM SRAM DRAM SDRAM DDR SDRAM

22. SRAM(Static RAM) Contents of SRAM remain permanent as long as power is given to it. We have to build about six transistors into each bit storage location. SRAM is quite fast as compare to DRAM. SRAM is about 10 times more expensive than DRAM. Time by time refreshment is not required. DRAM(Dynamic RAM) DRAM stores per bit data in single transistor and capacitor( in contrast to six transistors used in SRAM). Contents of DRAM remains in it only for few milliseconds because of tendency of capacitors to loose charge after this time. To overcome this limitation DRAM need continuous refreshment. Less expensive but slow data transfer rate as compare to SRAM.

23. SDRAM SDRAM synchronizes memory access to the CPU clock. While one portion of data transported to the CPU, another can be prepared for transfer. SDRAM uses 3.3v power signal generated by SMPS. SDRAM come with 168 pins SDRAM come with two notches. TimingActual SpeedData bus widthData Transfer Rate 15ns66MHz64bit528MBps 10ns100MHz64bit800MBps 8ns125MHz64bit1000MBps 7.5ns133MHz64bit1066MBps

24. DDR SDRAM DDR RAMs can transfer one data bit at rising edge one data bit at falling edge of the clock cycle as shown in fig. So it increase the transfer rate without increasing the frequency. DDR SDRAM consume 2.5v. DDR SDRAM come with 1 notch. Falling edge Rising Edge One clock cycle

25. SDRAMDDR Data Rate reads one words of data for each synchronous cycle reads two words of data for each synchronous cycle Voltage3.3 Volts2.5 Volts Speed66 MHz, 100 MHz, 133 MHz 200 MHz, 266 MHz, 333 MHz, 400 MHz Modules168-pin DIMM184-pin DIMM Release as 1 st generation DRAM 2 nd generation DRAM Data Strobes Two-NotchesSingle-Notch

26. DDR SDRAM

27. FEATURES OF PROCESSORS Pentium 2 features 1. Support for MMX technology MMX acronym for Multimedia Extensions OR Matrix Math Extensions as per whom you ask. MMX technology provide video compression, image manipulation, encryption and I/O processing features to Pentium 2. All these achieved by adding 57 new instructions in instruction set. 2.Pentium 2 processor come with two high speed cache L1 and L2 of size 32KB and 512KB respectively which increase the speed and performance.

28. 4. Built in FPU come with Pentium 2. 5. Pentium 2 can support reliability & integrity features by using Error Checking Code (ECC) signals. 6. Available with speed 233MHz to 450MHz. Celeron Processor features 1.Comes in speed from 333MHz to 2.6GHz. 2.As compare to P2, P3 Celeron have less size of L2 cache which increase the speed. 3.Celeron is a low cost processor due to reduced size of L2 cache.

29. DIB Architecture The Dual Independent Bus (DIB) architecture was first implemented in the sixth-generation processors from Intel and AMD. DIB was created to improve processor bus bandwidth and performance. Having two (dual) independent data I/O buses enables the processor to access data from either of its buses simultaneously and in parallel, rather than in a singular sequential manner (as in a single-bus system). Two buses make up the DIB architecture: the L2 cache bus and the main CPU bus, often called FSB (front side bus). The main (often called front-side) processor bus is the interface between the processor and the motherboard or chipset. The second (back-side) bus in a processor with DIB is used for the L2 cache, enabling it to run at much greater speeds than if it were to share the main processor bus.

30. The dual bus architecture enables the L2 cache of the newer processors to run at full speed inside the processor core on an independent bus, leaving the main CPU bus (FSB) to handle normal data flowing in and out of the chip. The two buses run at different speeds. The front-side bus or main CPU bus is coupled to the speed of the motherboard, whereas the back-side or L2 cache bus is coupled to the speed of the processor core. As the frequency of processors increases, so does the speed of the L2 cache. The P6 class processors, from the Pentium Pro to the Core 2, as well as Athlon 64 processors can use both buses simultaneously, eliminating a bottleneck there.Pentium Pro Athlon 64

31. Dual Independent Bus (DIB) Architecture

32. HYPER THREADING TECHNOLOGY Intel’s HT Technology allows a single processor or processor core to handle two independent sets of instructions at the same time. In essence, HT Technology converts a single physical processor core into two virtual processors. HT Technology was introduced on Xeon workstation-class processors with a 533 MHz system bus in March 2002. It found its way into standard desktop PC processors starting with the Pentium 4 3.06 GHz processor in November 2002.desktop PCPentium 4 HT Technology predates multicore processors, so processors that have multiple physical cores, such as the Core 2 and Core i Series, may or may not support this technology depending on the specific processor version. A quad-core processor that supports HT Technology (like the Core i Series) would appear as an 8-core processor to the OS; Intel’s Core i7-3970X has six cores and supports up to 12 threads. Internally, an HT-enabled processor has two sets of general-purpose registers, control registers, and other architecture components for each core, but both logical processors share the same cache, execution units, and buses. During operations, each logical processor handles a single thread.

34. Requirements for HT technology Processor supporting HT Technology—This includes many (but not all) Core i Series, Pen-tium 4, Xeon, and Atom processors. Check the specific model processor specifications to be sure. Compatible chipset—Some older chipsets may not support HT Technology. BIOS support to enable/disable HT Technology—Make sure you enable HT Technology in the BIOS Setup. HT Technology-enabled OS—Windows XP and later support HT Technology. Linux distributions based on kernel 2.4.18 and higher also support HT Technology. To see if HT Technology is functioning properly, you can check the Device Manager in Windows to see how many processors are recognized. When HT is supported and enabled, the Windows Device Manager shows twice as many processors as there are physical processor cores.

36. PCI PCI, or Peripheral Component Interconnect was developed by Intel in 1992 and is the local bus used in most PCs until know. PCI uses a shared bus topology to allow for communication among the different devices on the bus i.e. the different PCI devices are attached to the same bus, and share the bandwidth. It can run at clock speeds of 33 or 66 MHz. At 32 bits and 33 MHz, it will yield a throughput rate of 133 MBps which is too slow to cater for the latest frame grabbers especially as even this is shared with other PCI devices. This diagram explains the situation.

37. Fig. PCI Bus use shared bus topology

38. PCI-X stands for PCI Extended. The PCI-X spec essentially doubled the bus width from 32 bits to 64 bits, thereby increasing bandwidth. The PCI's basic clock rate is increased to 66MHz with a 133MHz variety on the high end, providing another boost to the bandwidth and bringing it up to 1GB/s (at 133MHz). Having said this PCI-X still suffers from the problem of Shared bus topology and also the faster a bus runs, the more sensitive it becomes to background noise. For this reason manufacturing standards for high-speed buses are exceptionally strict and therefore expensive. The PCI-x slot is physically longer than a PCI Slot.

39. PCI-E PCI-E stands fro PCI Express and is also known as 3GIO (Third Generation I/O) finally presented in 2002. The most fundamental improvement is the adoption of point-to-point bus topology. In a point-to-point bus topology, a shared switch replaces the shared bus as the single shared resource by means of which all of the devices communicate. Unlike in a shared bus topology, where the devices must collectively arbitrate among themselves for use of the bus, each device in the system has direct and exclusive access to the switch. a connection between two a PCIe device and a PCIe switch is called a link. Each link is composed of one or more lanes, and each lane is capable of transmitting one byte at a time in both directions at once.

40. Fig Point to point bus topology

42. AGP (Accelerated Graphics Port) A hardware interface from Intel for connecting a display adapter (graphics card) to a PC. Superseded by PCI Express, a single AGP slot on the motherboard provided a direct connection between the card and memory. AGP was introduced as a higher-speed alternative to PCI, and it freed up a PCI slot for another peripheral device. AGP is 32bit data path bus. The original AGP standard (AGP 1x) provided a data transfer rate of 264 MB/sec. AGP 2x, 4x and 8x increased the rate to 528 MB/sec, 1 GB/sec and 2 GB/sec.

44. LOGICAL MEMORY ORGANIZATION Conventional Memory It consist DOS interrupt vector, Device Drivers, Command shell, TSR Upper memory The upper memory area (UMA) is memory in the range between 640 kb and 1 Mb. By default there is no RAM in this range as it is reserved for use with hardware that is able to map own memory to this range. Usually present in this region is a part of the graphics cards RAM and the BIOS ROMs of the graphics card and mainboard. Higher Memory Accessed in real mode, Used as more conventional memory area.

46. Cache memory A small and very fast memory storage located between the PC’s primary memory (RAM) and its processor. Cache memory holds copies of instructions and data that it gets from RAM to provide high speed access by the processor. SRAM and cache memory Cache memory is usually a small amount of static random access memory or SRAM. SRAM is made up of transistors that don’t need to be frequently refreshed (unlike DRAM, which is made up of capacitors and must be constantly refreshed). SRAM has access speeds of 2ns (nanoseconds) or faster; this is much faster than DRAM, which has access speeds of around 50ns. Data and instructions stored in SRAM-based cache memory are transferred to the CPU many times faster than if the data were transferred from the PC’s main memory.

47. Why SRAM is not used as Primary Memory In case you’re wondering why SRAM isn’t also used for primary memory, which could eliminate the need for cache memory all together, there are some very good practical and economic reasons SRAM costs as much as six times more than DRAM and to store the same amount of data as DRAM would require a lot more space on the motherboard. Level 1 cache : Level 1cache is often referred to interchangeably with internal cache, and rightly so. L1cache is placed internally on the processor chip and is, of course, the cache memory closest to the CPU. Level 2 cache: Level 2 cache is normally placed on the motherboard very near the CPU, but because it is further way then L1 cache, it is designated as the second level of cache. Commonly, L2 cache is considered the same as external cache, but L2 cache can also be included on the CPU chip. If there is a level 3 to cache, it is RAM.

50. BIOS BIOS ROM occupies 128KB of space in the systems Upper Memory Area (UMA) from E0000h to FFFFFh. BIOS are designed with ROM,EPROM or EEPROM. BIOS is a program executes and load its sections in main memory even before loading operating system. A program known as BOOTSTRAP is used to load operating system in main memory. BIOS contains 3 sections as shown in following figure. POST System Routines CMOS SETUP ROUTINE

51. POST POST is a acronym for Power-On-Self-Test. POST is actually a program that performs a low level diagnostic and reliability test of the main processing components – eg Processor, RAM, Motherboard chipset. POST also set up a index for interrupt vectors for the CPU. CMOS SETUP ROUTINE CMOS ( Complementary Metal Oxide Semiconductor ) is a RAM chip of small size contains hardware configuration parameters. To access a system’s configuration a CMOS SETUP ROUTINE is required. SYSTEM SERVICE ROUTINES These are the routines work as a interface between hardware devices and operating system.

52. Motherboard Selection Criteria Following are some criteria's for selection of motherboard Motherboard chipset. Motherboard speed Motherboard bus type Processor Processor Sockets Built in interfaces