1. 65nm CMOS Foundry Services
Sandro Bonacini, Kostas Kloukinas, Alessandro Marchioro
ATLAS Upgrade Week: Electronics Meeting
Wednesday, 6 November 2013

2. Outline Overview of supported ASIC design technologies
News on 65nm Technology
Contractual aspects
Commercial
Legal
Technical aspects
06/11/13

3. Supported Technologies
CMOS 6SF
Legacy designs
CMOS 8RF-DM
Low cost technology for
Analog & RF designs
CMOS 8RF-LM
Low cost technology for
Large Digital designs
BiCMOS 8WL-HP High Performance technology for demanding RF designs
CMOS 9SF LP/RF
High performance technology for dense designs
Foundry A
250nm CMOS
130nm CMOS
90nm CMOS
Active technology nodes:
Legacy technology: CMOS6SF 250nm
Mainstream technology: CMOS8RF 130nm
95% of ASIC projects on DM variant
Advance technology: CMOS 65nm
For LHC upgrade applications.
Alternate technology: CMOS 130nm
CMOS 65nm
High performance technology for dense designs
CMOS 130nm
Cost efficient technology for
Analog & RF designs
Foundry B
65nm CMOS
130nm CMOS
06/11/13

4. Foundry Services News Contract with Foundry A Contract with Foundry B
Contract renewed for 3 years ( )
Same pricing conditions apply with some minor changes
Confidential Disclosure Agreement (CDA) with institutes will expire by the end of 2013
Renewal procedure in progress Institute signatory authorities are being contacted by
Contract with Foundry B
Foundry access via an intermediary silicon broker: Europractice, IMEC
Contract preparation is in the final stage
Long procedures for negotiating technology information disclosure legal terms and contractual pricing conditions for prototyping and production services
Contract covers a period of 5 years ( )
06/11/13

5. Commercial aspects 65nm tech.
All prices are fixed and accepted by CERN
Because of the many complicated technology “options” available, the preparation of a final pricing table was a lengthy procedure.
Prototype price is in line with expectations
Technology options modulate strongly the prototyping cost.
Production price is remarkably LOW !
06/11/13

6. Legal aspects Non Disclosure Agreement (NDA)
3-party NDA: Foundry - IMEC – Institute
Permitting the distribution of technology data, including layouts of std. cell libraries
Permitting institutes to exchange technical data and work in collaboration
Covers both 65nm and 130nm processes
Confidentiality of technical data and documentation
Technology data should reside in institutes secure servers and workstations
Issue of accessing technology remotely) is still hotly debated and unresolved
Portable devices storing foundry documentation shall use encrypted storage
Allows use for some applications outside HEP
Space applications for “scientific research” and “radiation monitoring”
Nuclear applications for “hospital diagnostic” and “material analysis”. Nuclear power and military is excluded.
Automotive applications is currently not allowed but can be renegotiated on case-by-case basis.
Sale of chips is permitted except for banned applications
Export control restrictions apply as for Foundry A
06/11/13

7. Legal aspects
All NDAs issued by IMEC are identical. Neither IMEC nor the foundry are willing to negotiate 35+ times with all single Institutes
Previous NDAs signed between IMEC and Institutes will be invalidated prior to entering the new scheme.
The list of signatories will be made accessible so that everybody knows if working with a “validated” partner
IMEC will not accept submission under the CERN contract from Institutes with the “old” NDA in place
One delicate point is still under discussion between lawyers and has to do with the responsibility of individuals in case of breach of confidentiality
06/11/13

8. Mixed Signal Design kit
Technical aspects
Motivation to Develop & Distribute a 65nm Mixed Signal Design kit
Advanced Technology
stricter layout design rules, many technology options, complex process simulation techniques
Modern CAE tools
Powerful and flexible CAE Tools but complicated to use.
Increased complexity Designs
HEP designs are gradually turning into Systems On Chips (SOC)
Costly Technology
First silicon success
Exchange of IP blocks between design teams
Complex Design Environment
Projects with large, fragmented, multinational design teams.
Designers with different levels of design expertise.
Development of a 65nm Mixed Signal design kit
Integrating digital standard cell libraries including the physical layouts
Establish well defined Analog & Mixed Signal design workflows.
Implemented on modern versions of CAE Tools compatible with EUROPRACTICE releases
Development work done by CERN & Cadence
Currently in “beta” testing. Target release date: end of November 2013.
Mixed Signal Design kit
PDK
Digital Libs
Flow
Design workflows
06/11/13

9. Mixed Signal design kit contents
N65OA
V1.7A_1_VCAD 3x1z1u
V1.7A_1_VCAD 6x1z1u
Calibre
PVS
Libraries …
tsmcN65
PDK_doc
models
7-tracks hVt
std cells
9-tracks std cell
IO Pads
06/11/13

10. Mixed Signal Designs flows
Analog
Schematic entry
Analog
simulation
Full-custom layout
Parasitic extraction
Analog
simulation
M/S
simulation
Abstract generation
M/S
simulation
Signoff
Digital
HDL code
Digital
simulation
Synthesis P&R
Parasitic extraction
Digital simulation
Develop and validate design flows to allow analog and digital design interoperability.
06/11/13

11. Supported metal stacks and libraries
CERN Mixed Signal design kit will be supported for:
2 metal stacks
6+1 metals (“CERN metal stack”)
4-thin, 1-thick, 1-UTM , RDL
9+1 metals (compatible with IMEC
7-thin, 1-thick, 1-UTM , RDL
+ 220 k$ for mask set (!)
2 choices of std. cell libraries
9-tracks, standard-Vt
tcbn65lp
7-tracks, high-Vt
Tcbn65lpbwp7thvt
“Special” metal stack require special PDK.
This will require a one-time-charge of 15-20KEuro
+ annual maintenance for the requesting project
Institutes can always get organized to share costs of special PDKs among themselves.
STI
poly M2 M1 M3 M5 M6 M4 W
RDL
passivation
mimcap
06/11/13

12. Mixed Signal Design kit Distribution
Distribution of package to institutes done by IMEC (Europractice)
Sign NDA with institutes
Distribute the Design kit and workflows
Provide maintenance and updates in collaboration with VCAD
Foundry
IMEC
Cadence VCAD design services
CERN
Physics institutes
06/11/13

13. Training: M/S kit Workshops
A series of Training Workshops for 65nm CMOS will be organized
To present the Mixed Signal Kit.
To present Analog, Digital and Mixed Signal design Workflows.
Scheduled for February 2014
At IMEC or at CERN
Cadence (VCAD) design services team:
Will prepare the training lectures and the accompanying documentation
Will provide engineers to lecture in the courses.
3 days training with lectures and hands-on design exercises
Workshop modules based on a realistic Mixed Signal Design
Training material (scripts, design examples and documentation) made available to participants.
Example Mixed Signal ASIC:
“8-bit DAC with I2C serial interface”
06/11/13

14. Foundry Access Services
CERN
Physics institutes
Foundry Access
All submissions must go via IMEC
MPW as scheduled from IMEC and foundry
CyberShuttle
metal stack
6-thin, 1-thick, 1-UTM
Additional runs for HEP
Metal stack 4-thin, 1-thick, 1-UTM
Possibly every 4 months?
Engineering/production runs
Physics institutes to send the purchase order via CERN
GDS will be submitted directly to IMEC
IMEC
Foundry
06/11/13

15. Foundry Services News
CERN can not engage in a manpower demanding, long term maintenance program as in the past
Users should start thinking having IMEC as a support center, but not for free.
Contacts at CERN for foundry services
Gert Olesen
Kostas Kloukinas
Generic address: Please use this address for foundry access requests
06/11/13

16. Thank You
06/11/13

17. 130 nm Mixed Signal Kit Distribution
Italy
INFN Rome
INFN Torino
INFN Bologna
INFN Bari
INFN Cagliari
Univ. of Bergamo
Univ. of Pisa
Univ. of Pavia
Polytecnico di Milano US
Brookhaven Lab.
Columbia University
Fermilab
Lawrence Berkeley Lab.
Rutgers Univ.
Univ. of Chicago
Univ. of Hawaii
Univ. of Pennsylvania
Ohio State University
SMU,Dallas
Santa Cruz Institute
France
CEA SACLAY, Paris
IN2P3, Paris
LPNHE, Paris
IPNL, Lyon
IPHC, Strasbourg
LPSC, Grenoble
LAPP, Annecy
LPC, Clermont-Ferrand
CPPM, Marceille
INPG, Grenoble
Germany
Bergische Universität Wuppertal
DESY, Hamburg
Institut der Universitaet Heidelberg
Max-Plank-Institute fur Physik
Max-Plank-Institute Halbleiterlabor
Forschungszentrum Julich
University of Siegen
Universität Bonn UK
Rutherford Appleton Lab.
Imperial College London
University College London
Oxford University
CERN
Portugal
INESC, Porto
LIP, Lisbon
Switzerland
Universite de Geneve
Spain
Univ. of Barcelona
IFAE, Barcelona
IFIC, Valencia
Netherlands
NIKEF, Amsterdam
Poland
AGH Univ. of Science & Tech.
06/11/13

18. 130nm Technical Support Foundry Physical IP vendors CAE Tools vendors
Compiles and Distributes the 130nm Mixed Signal Design kit
Provide maintenance and technical support to the collaborating institutes.
CERN CAE tools & technology support
Cadence VCAD design services
CERN designers
External designers
06/11/13

19. 130nm Foundry Access Service
CERN designers
External designers
CERN Foundry Services
CERN organizes MPW runs among the collaborating institutes to help in keeping low the silicon prototyping costs.
Foundry
MOSIS
06/11/13

20. 130nm MPW activity
CERN participates on all MOSIS MPW runs (4 runs/year) and organizes ad-hoc MPWs directly with the foundry for high volume and/or area demanding designs
Prototyping and Engineering run costs are kept the same for the last 2 years.
Evolution of the Prototyping activity on CMOS8RF for the last 6 years
CMOS8RF-DM (3-2-3) is the dominant metal stack
06/11/13