1. 3D ASICs program at Fermilab Fermilab ASIC Design Group (G.Deptuch, F.Fahim, J.Hoff, M.Trimpl, A.Shenai, T.Zimmerman) R.Yarema – retired D.Christian, R.Lipton, T.Liu and collaborators from: BNL Upton NY, SLAC Menlo Park CA, AGH-UST Kraków Poland US Universities: Brown U., Cornell U. and industrial partners: Tezzaron Naperville IL, Ziptronix Morrisville NC, RTI Research Triangle Park NC, ALLVIA Sunnyvale CA, CVInc. Dallas TX,

2. Introduction 2 AEM Nov. 4, 2013 Environment of integrated circuits technology for radiation detector readout systems is: Competitive Investments hungry Characterized by long gaining experience curves for the ASIC groups Challenging due to restrictions in access to the cutting edge technologies, legalities and bureaucratic burden associated with it Groups tend to emphasize on one or a few particular detector technologies, families of design blocs, design methodologies or assembly works and excel offering complementary sets of skills and tools to the community

3. 3D chip is composed of two or more layers of active electronic components and features horizontal intra-tier and vertical inter-tier connectivity, Distinguishing features of 3D technologies:  Through Silicon Vias (TSV)  Bonding  Wafer thinning  Back-side processing  Transformational change:  Finer pitch pixels  Less mass  Higher localized “on detector” functionality  Bump bond alternative  Non dead space arrays  3 Motivation Strategic goal: 4 side buttable, dead-area-free detectors for uses ranging from X-ray, visible, IR imaging to classical tracking AEM Nov. 4, 2013

4. 4 Review: design VIP2b AEM Nov. 4, 2013

5. 5 Review: design VICTR AEM Nov. 4, 2013

6. Review: design VIPIC1 6 AEM Nov. 4, 2013

7. VIPIC1 (Prototype) is designed to quickly count the number of hits in every pixel and read out the # of hits, and addresses in a dead timeless manner, 7 Design of VIPIC1 - 1 G.Deptuch, M.Demarteau, J.Hoff, R.Lipton, A.Shenai, M.Trimpl, et al., “Vertically Integrated Circuits at Fermilab“, IEEE Transaction on Nuclear Science, vol. 57, no. 4, (2010), pp. 2178-2186 G.Deptuch, M.Trimpl, R.Yarema, D.P.Siddons, G.Carini, R.Szczygieł, P.Grybos, P.Maj, “VIPIC IC - Design and Test Aspects of the 3D Pixel Chip”, Proceedings of Nuclear Science Symposium, Knoxville, USA, October 2010 G.Deptuch, G.Carini, P.Gryboś, P.Kmon, P.Maj, M.Trimpl, D.P.Siddons, R.Szczygieł, R.Yarema, „Design and Tests of the Vertically Integrated Photon Imaging Chip” – submitted to IEEE Transaction on Nuclear Science AEM Nov. 4, 2013

8. Digital:1400 transistorsAnalog: 280 transistors discriminator output 12-bit for configuration 7-bit trim offset, 3-bit trim R f, single/dif mode, CAL enable Doubled bond pads for each signal Power suplies tied between tiers  in-pixel 1-stage pipe-line logic  disributed sparsifier: 8 bit priority encoder, pixel readout selector, pixel address generator and counter output  2×5-bit long counters  configuration registers: single bit / pixel (pixel SET, pixel RESET) and 12 bit DAC and configuration (calib., singl./diff.) 8 Design of VIPIC1 - 2  Single ended or pseudo- differential CSA-shaping filter- discriminator: shaping time  p =250 ns, power ~25  W / analog pixel, noise <150 e - ENC, gain(C feed =8fF) = ~115mV/8keV (optimized for 8 keV in Si - linearity up to 3×8 keV)  1 threshold discriminator  10 bit/pixel DAC adjustments 2-lines for CAL circuits AEM Nov. 4, 2013

9. 9 3D-IC Consortium established in late 2008, 17 members; 6 countries + Tezzaron Fermilab set up 1 st 3D-IC MPW for HEP-MPW frame accepted for fab in 03/2010 1 st working chips got from 2 bonded pairs of wafers (TC) in 06/2012 March-May-June 2013 last 3D bonded wafers (TC and DBI) yielding more good chips Face-Face TS Vias (  =1  m) Fabrication of VIPIC1 - 1 1 st 3D-IC MPW RUN Tezzaron / Novati Ziptronix / licensed to Novati AEM Nov. 4, 2013

10. Tests VIPIC1 electrical - 1 10 Map of pixels with noise (scale: black – 0 mV rms, white – 10 mV rms)  Hamamatsu baby sensors available as singulated dies, decided to be used while waiting for ultimate bonding of BNL sensors using the DBI process Layout of ”to sensor pads” on VIPIC1 original 80  m - pitch pads for BNL sensors overlaid with 100  m pitch pads for Hamamatsu sensors 80  m pitch 100  m pitch skipped row skipped column Noise (ENC) calculated using gain from calibration with charge injection AEM Nov. 4, 2013

11. 11 Tests VIPIC1 bump bonded to sensor - 1  100  m pitch Hamamatsu pixel baby- sensor with Sn-Pb bumps  deposition technique on a single die with ENIG UBM on Al substrate pads by (CVInc.) – pads  =60  m  UBM deposited on VIPIC (ENIG pads are bondable)  300  m thick Hamamatsu pixel sensor mounted on top of VIPIC (75  m bump, post reflow gap at 45  m to 50  m prior to addition of underfill)  Optimization of the Ni-Au deposition led to almost 100% of pads retaining UBM and bumps 500  m thick back-side of sensor Wire bonding pads AEM Nov. 4, 2013

12. 12 Tests VIPIC1 bump bonded to sensor - 2 Detector biased at 120 V (full depletion) 109 Cd and 55 Fe used W mask with Fermilab logo ROIC area rows & cols skipped 2G 2  55 Fe source used  All signals integrated above threshold set higher than noise  Only very limited number of pixels are insensitive  significant gain dispersions  Full sparsified readout (from all 16 groups of 4×64 pixels) used  Acquisition run for a few hours to accumulate enough of statistics Transmission radiogram of a small W mask (2.5×2.5 mm 2 ) placed atop of the sensor back- side illuminated and fully depleted mask has features smaller than the sensor pitch, e.g. center hole  =75  m AEM Nov. 4, 2013

13. 13 Tests VIPIC1 bump bonded to sensor - 3  Scanning of thresholds (vt2-vt1) with fine 0.5 mV/step resolution  Full sparsified readout using 50 MHz data serialization clock simultaneously from every group  Duration of a single readout cycle ~80  s (timing precision)  Reference data without source  Sources used: - 109 Cd 22 keV (1mCi) - 55 Fe 5.9 keV (10mCi) Detector biased at 120 V (full depletion) 109 Cd 22keV and 55 Fe 5.9keV  5.9 keV photon  1640 e - /h + Gain= (420-350) mV/ph*1ph/1640=43  V/e - Noise= 3.5 mV rms*1e - /43  V = 83e - rms Response gets strongly nonlinear above approximately 18 keV Selected results from a single pixel from a run with flat field illumination Definite analyses (noise, gain, statistics) are underway… as well as devices bonded to 64 ×64 pixel sensors are expected before the end of 2013 AEM Nov. 4, 2013

14. 14 Invitation AEM Nov. 4, 2013

15. 15 Invitation AEM Nov. 4, 2013