1. Chapter 10 The Stack l Stack data structure l Interrupt I/O l Arithmetic using a stack

2. 2 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly Stack Data Structure l Abstract Data Structures – are defined simply by the rules for inserting and extracting data l The rule for a Stack is LIFO (Last In - First Out) – Operations: l Push (enter item at top of stack) l Pop (remove item from top of stack) – Error conditions: l Underflow (trying to pop from empty stack) l Overflow (trying to push onto full stack) – We just have to keep track of the address of top of stack (TOS)

3. 3 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly A “physical” stack l A coin holder as a stack

4. 4 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly A hardware stack l Implemented in hardware (e.g. registers) – Previous data entries move up to accommodate each new data entry l Note that the Top Of Stack is always in the same place.

5. 5 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly A software stack l Implemented in memory – The Top Of Stack moves as new data is entered l Here R6 is the TOS register, a pointer to the Top Of Stack

6. 6 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly Push & Pop l Push – Decrement TOS pointer (our stack is moving down) – then write data in R0 to new TOS l Pop – Read data at current TOS into R0 – then increment TOS pointer PUSHADDR6, R6, # -1 STRR0, R6, # 0 POPLDRR0, R6, # 0 ADDR6, R6, # 1

7. 7 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly Push & Pop (cont.) l Push – Decrement TOS pointer (our stack is moving down) – then write data in R0 to new TOS l Pop – Read data at current TOS into R0 – then increment TOS pointer l What if stack is already full or empty? – Before pushing, we have to test for overflow – Before popping, we have to test for underflow – In both cases, we use R5 to report success or failure

8. 8 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly PUSH & POP in LC-3 PUSH STR2, Sv2 ;needed by PUSH STR1, Sv1 ;needed by PUSH LDR1, MAX;MAX has -x3FFB ADDR2, R6, R1 ;Compare SP to x3FFB BRzfail_exit;Branch is stack is full ADDR6, R6, # -1;Adjust Stack Pointer STRR0, R6, # 0;The actual ‘push’ BRnzp success_exit … BASE.FILL xC001 ;Base has -x3FFF MAX.FILL xC005 ;Max has -x3FFB Sv1.FILL x0000 Sv2.FILL x0000 x3FFB MAX … x3FFF BASE

9. 9 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly PUSH & POP in LC-3 POP STR2, Sv2 ;save, needed by POP STR1, Sv1 ;save, needed by POP LDR1, BASE;BASE contains x-3FFF ADDR1, R1, # -1 ;R1 now has x-4000 ADDR2, R6, R1 ;Compare SP to x4000 BRzfail_exit;Branch if stack is empty LDRR0, R6, # 0 ;The actual ‘pop’ ADDR6, R6, # 1 ;Adjust stack pointer BRnzp success_exit … BASE.FILL xC001 ;Base has -x3FFF MAX.FILL xC005 ;Max has -x3FFB Sv1.FILL x0000 Sv2.FILL x0000

10. 10 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly PUSH & POP in LC-2 (cont.) success_exitLDR1, Sv1 ;Restore register values LDR2, Sv2 ; ANDR5, R5, # 0;R5 <-- success RET ; fail_exit LDR1, Sv1;Restore register values LDR2, Sv2 ANDR5, R5, # 0 ADDR5, R5, # 1;R5 <-- fail RET BASE.FILL xC001 ;Base has -x3FFF MAX.FILL xC005 ;Max has -x3FFB Sv1.FILL x0000 Sv2.FILL x0000

11. 11 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly Memory-mapped I/O revisited

12. 12 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly Interrupt-driven I/O l Just one device: CPU Memory I/O IRQ IACK l When IRQ goes active, jump to a special memory location: the ISR, or interrupt service routine. For now, let’s say it exists at address x1000. l Activate IACK to tell the device that the interrupt is being serviced, and it can stop activating the IRQ line.

13. 13 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly Generating the Interrupt l Using the Status Register – The peripheral sets a Ready bit in SR[15] (as with polling) – The CPU sets an Interrupt Enable bit in SR[14] – These two bits are anded to set the Interrupt. l In this way, the CPU has the final say in who gets to interrupt it!

14. 14 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly Processing an interrupt: one device l Device generates an IRQ l CPU signals IACK – “OK, I’m on it.” l Switch to Supervisor Mode l CPU saves its current state –What and how? l Address of the ISR is loaded into the PC –x1000 l Continue – process the interrupt l When finished, return to running program –How?

15. 15 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly Supervisor Mode l Bit 15 of the PSR = Privileged (supervisor) mode Priv PriorityNZP 1510 – 8210210 l Only the Operating System can access device addresses Why?

16. 16 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly Interrupts and program state l We need to save the PC, the PSR, and all Registers –We could require that ISRs save all relevant registers (callee save) –The callee would ALWAYS have to save the contents of the PC and PSR l In most computers these values (and possibly all register contents) are stored on a stack –Remember, there might be nested interrupts, so simply saving them to a register or reserved memory location might not work.

17. 17 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly The Supervisor Stack l The LC-3 has two stacks –The User stack l Used by the programmer for subroutine calls and other stack functions –The Supervisor stack l Used by programs in supervisor mode (interrupt processing) l Each stack is in separate region of memory l The stack pointer for the current stack is always R6. –If the current program is in privileged mode, R6 points to the Supervisor stack, otherwise it points to the user stack. l Two special purpose registers, Saved.SSP and Saved.USP, are used to store the pointer currently not in use, so the two stacks can share push/pop subroutines without interfering with each other.

18. 18 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly Saving State l When the CPU receives an INT signal … –If the system was previously in User mode, the User stack pointer is saved & the Supervisor stack pointer is loaded l Saved.USP <= (R6) l R6 <= (Saved.SSP) – PC and PSR are pushed onto the Supervisor Stack – Set the system to Supervisor mode l PSR[15] <= 0 l Jump to the interrupt service routine

19. 19 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly Processing an interrupt: details l Device generates in IRQ l CPU signals IACK – “OK, I’m on it.” l CPU saves its current state –PC and PSR are saved on the Supervisor Stack l Switch to Supervisor Mode –Change the S bit in the PSR to 0. l Address of the ISR is loaded into the PC –For now we assume just one ISR – x1000 l Continue – process the interrupt l When finished, return to running program –Pop the PC and PSR from the Supervisor Stack

20. 20 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly More than one device l Who sent the interrupt? l One way is to have a unified ISR that checks the status bits of every device in the system –This is a hybrid method between interrupt-driven I/O and polling –Requires every new device to modify the ISR –The ISR will be large and complex CPU Memory I/O 1 IRQ I/O 2I/O 3I/O 4

21. 21 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly Vectored Interrupts l If we have multiple devices, we need a very large ISR that knows how to deal with all of them! l Using vectored interrupts, we can have a different ISR for each device. l Each I/O device has a special register where it keeps a special number called the interrupt vector. –The vector tells the CPU where to look for the ISR.

22. 22 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly A vectored-interrupt device x8002 x8000 x8004 Input register Output register Device Controller Status register x8006 Interrupt Vector Register 67 When I trigger an interrupt, look up address number 67 in the vector table, and jump to that address.When I trigger an interrupt, look up address number 67 in the vector table, and jump to that address.

23. 23 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly Getting the interrupt vector l INTA tells a device to put the interrupt vector on the bus l INTA is daisy chained so only one device will respond CPU Memory I/O 1I/O 2I/O 3I/O 4 IRQ INTA

24. 24 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly Initial state of the ISR l Vectored interrupts – Along with the INT signal, the I/O device transmits an 8-bit vector (INTV). – If the interrupt is accepted, INTV is expanded to a 16-bit address: l The Interrupt Vector Table resides in locations x0100 to x01FF and holds the starting addresses of the various Interrupt Service Routines. (similar to the Trap Vector Table and the Trap Service Routines) l INTV is an index into the Interrupt Vector Table, i.e. the address of the relevant ISR is ( x0100 + Zext(INTV) ) – The address of the ISR is loaded into the PC – The PSR is set as follows: l PSR[15] <= 1 (Supervisor mode) l PSR[2:0] <= 000 (no condition codes set) l Now we wait while the interrupt is processed

25. 25 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly Interrupt sequence: >1 device l Device generates an IRQ l CPU switches to SSP if necessary (hardware) l Current PC and PSR are saved to the supervisor stack (hardware) l Switch to supervisor mode (S = 0; hardware) l CPU sends IACK, which is daisy chained to device (hardware) l Device sends its vector number (hardware) l Vector is looked up in the interrupt vector table, and address of the ISR is loaded into the PC (hardware) l ISR saves any registers that it will use (software) l ISR runs, then restores register values (software) l ISR executes RTI instruction, which restores PSR and PC (software) –Note that this restores previous supervisor/user mode

26. 26 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly Multiple devices: priority l What happens if another interrupt occurs while the system is processing an interrupt? l Can devices be “starved” in this system?

27. 27 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly Priority l Each task has an assigned priority level – LC-3 has levels PL0 (lowest) to PL7 (highest). – If a higher priority task requests access, then a lower priority task will be suspended. l Likewise, each device has an assigned priority –The highest priority interrupt is passed on to the CPU only if it has higher priority than the currently executing task. l If an INT is present at the start of the instruction cycle, then an extra step is inserted: –The CPU saves its state information so that it can later return to the current task. –The PC is loaded with the starting address of the Interrupt Service Routine –The FETCH phase of the cycle continues as normal.

28. 28 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly Priority of the current program l Remember those extra bits in the PSR? Priv PriorityNZP 1510 – 8210210

29. 29 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly Device Priority

30. 30 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly Returning from the Interrupt l The last instruction of an ISR is RTI (ReTurn from Interrupt) – Return from Interrupt (opcode 1000) – Pops PSR and PC from the Supervisor stack – Restores the condition codes from PSR – If necessary (i.e. if the current privilege mode is User) restores the user stack pointer to R6 from Saved.USP l Essentially this restores the state of our program to exactly the state it had prior to the interrupt –Continues running the program as if nothing had happened! l How does this enable multiprogramming environments?

31. 31 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly The entire interrupt sequence l Device generates an IRQ at a specific PL l IF requesting PL > current process priority: –CPU switches to SSP if necessary (hardware) –Current PC and PSR are saved to the supervisor stack (hardware) –Switch to supervisor mode (S = 0; hardware) –Set process priority to requested interrupt PL –CPU sends IACK, which is daisy chained to device (hardware) –Device sends its vector number (hardware) –Vector is looked up in the interrupt vector table, and address of the ISR is loaded into the PC (hardware) –ISR saves any registers that it will use (software) –ISR runs, then restores register values (software) –ISR executes RTI instruction, which restores PSR and PC (software) l Note that this restores previous supervisor/user mode and process priority

32. 32 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly Execution flow for a nested interrupt

33. 33 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly Supervisor Stack & PC during INT

34. 34 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly Interrupts: Not just for I/O l Interrupts are also used for: –Errors (divide by zero, etc.) –TRAPs –Operating system events (quanta for multitasking, etc.) –User generated events (Ctrl-C, Ctrl-Z, Ctrl-Alt-Del, etc.) –…and more.

35. 35 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly DMA – Direct Memory Access l DMA –A device specialized in transferring data between memory and an I/O device (disk). –CPU writes the starting address and size of the region of memory to be copied, both source and destination addresses. –DMA does the transfer in the background. –It accesses the memory only when the CPU is not accessing it (cycle stealing). I/O Dev CPU memory DMA

36. 36 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly Stack-based instruction sets l Three-address vs zero-address – The LC-3 explicitly specifies the location of each operand: it is a three- address machine l e.g. ADD R0, R1, R2 –Some machines use a stack data structure for all temporary data storage: these are zero-address machines l the instruction ADD would simply pop the top two values from the stack, add them, and push the result back on the stack l Most calculators use a stack to do arithmetic, most general purpose microprocessors use a register bank l Two-address machines –This has nothing to do with stacks… but the x86 is a two-address machine –The DR is always SR1 –So ADD R0, R1 in x86 is equivalent to ADD R0, R0, R1 in LC-3 –Implications?

37. 37 College of Charleston, Computer Science Dr. Anderson CS 250 Comp. Org. & Assembly Practice problems l 10.8, 10.10 (this is a good one!), 10.12 (long, but good), 10.13 (also long, but good)