1. Counting with Sequential Logic Experiment 8

2. Experiment 7 Questions 1. Determine the propagation delay (in number of gates) from each input to each output for the half adder. One gate delay maximum. 2. Determine the propagation delay (in number of gates) from each input to each output for the full adder. Two gates delays. 3. How many rows would there be in the truth table for a 4-bit binary adder? 32 rows How many input and output variables are there? 8 input; 5 output Would it be feasible to design a 32-bit adder using this technique? Not in this lifetime 4. How many logic gates are needed to build the 4-bit ripple carry adder? 2 + 3*6 = 20 What is the worst case delay path through the 4-bit ripple carry adder? When a carry propagates through each of the bits. What 4-bit input values cause the worst case delay? 1111 + 0001 (and others) 5. List the number of gate delays that are on the critical path? 4-bit RCA = 7 gates delays How many gate delays would there be in an 8-bit ripple carry adder? 15 gate delays. 6. How many gate delays would there be in an n-bit ripple carry adder? 2(n-1) + 1 How would you modify your 4-bit ripple carry adder to make an adder/subtractor? Change half adder to full adder, be able to complement one operand (2’s complement approach).

3. Experiment 7 Comments Directly reference figures and tablesDirectly reference figures and tables Indirectly reference VHDL code and timing diagramsIndirectly reference VHDL code and timing diagrams Efficiency of Ripple carry adderEfficiency of Ripple carry adder –time efficient? NO –space efficient? YES

4. Instructional Objectives: To use sequential VHDL statements in the design of a T flip-flopTo use sequential VHDL statements in the design of a T flip-flop –Creating “memory” with VHDL code –Handling feedback of output signals –Using intermediate signals and initialization To design a T-FF based 4-bit counter using a Structural VHDL design approachTo design a T-FF based 4-bit counter using a Structural VHDL design approach To apply a modular design approach to integrate and test the counterTo apply a modular design approach to integrate and test the counter

5. Sequential Storage Elements Combinational vs. Sequential Circuits –Combinational: cannot store information Outputs a function of inputs –Sequential: stores information (bits) Outputs a function of inputs and current outputs Sequential Circuits: considered to have states –State of circuit: based on what is being stored by circuits storage elements –Sequential circuits = finite state machines (FSMs)

6. Basic Bit-Storage Elements Latches –Cross coupled cells: NOR and NAND –state changes when inputs change Gated latches (add a clock) –State changes on active level of clock –Level sensitive devices Flip-flops –State changes only on active edge of clock signal RET (rising-edge triggered devices) FET (falling-edge triggered devices)

7. D Flip-flop A D flip-flop changes its current state Q at the rising edge of a clock signal. It’s new state is given by the characteristic equation of the D flip-flop: Q + = D (Q + = next state of circuit) entity d_ff_x is port ( D : in std_logic; CLK : in std_logic; Q : out std_logic); end d_ff_x; architecture my_d_ff of d_ff_x is begin dff: process (D, CLK) begin if (rising_edge(CLK)) then Q <= D; end if; end process dff; end my_d_ff;

8. T Flip-flop A T flip-flop toggles its current state Q at the rising edge of a clock signal. It’s new state is given by the characteristic equation of the T flip-flop: Q + = T XOR Q (Q + = next state of circuit) Your T flip-flop will include an active high EN able T EN CLKTQ+Q+ 0--Q (hold) 1↑0 1↑1 not Q (toggle)

9. Making a T Flip-Flop Q CLK T Characteristic Equation Using a D Flip Flop And Additional Gates Q CLK D ? T TQQ+Q+ Action 000Hold 011 101Toggle 110 TQ D Needed Q+Q+ Action 000Hold 011 101Toggle 110 1) What “D” values are needed to produce the desired “Q + ” values for the given “Q’s”? - Based on the behavior of the D flip-flop 0 1 1 0 2) Determine logic expression for D in terms of T (input), and Q (present output) Desired Behavior

10. VHDL Sequential Statements ARCHITECTURE my_arch OF myhalfadder IS BEGIN PROCESS (sensitivity list) BEGIN sequential statement 1; sequential statement 2; END PROCESS; END my_arch;

11. 4- Synchronous Bit Binary Counter ?? Output of 4 Flip-Flops Form a 4-Bit Binary COUNT The COUNT Should Increment in A Binary # Sequence 0000  0001  The COUNT Should Increment On Each Rising Edge of The CLK The ENable Should Make the Count Increment (EN=1) Or Hold (EN=0)

12. 3-Bit Synchronous Binary Up Counter Output Count Output Y 2 Output Y 1 Output Y 0 0000 1001 2010 3011 4100 5101 6110 7111 0000 Toggle Y 0 “toggles” every count (every clock cycle) Y 1 “toggles” every 2 counts (What conditions precede all toggles?) Y 2 “toggles” every 4 counts (What precedes?)

13. Designing Counter Set up the sequence of all possible “ count ” outputs –In standard truth table order Write the next “ count ” output value beside each “present output” in the Table For each Flip-Flop output (Q), ask: –What are the specific PRESENT OUTPUT (Q) and NEXT OUTPUT (Q + ) values needed for the desired sequence in each row of the Table? –What input value (T) is needed on the T Flip-Flop producing that output, in order to generate the needed NEXT OUTPUT (Q+) for that row when the proper clock edge occurs?... Given that the output has its PRESENT value (Q) at the moment –What Boolean Logic combination of the PRESENT OUTPUTS (Q 0, Q 1, Q 2,..) will give you those needed values of “T” ?

14. 4- Synchronous Bit Binary Counter You know how you want the Flip-Flop outputs to change… …then determine what Flip-Flop inputs are needed to get the needed output changes… …and design the combinational circuits to generate those inputs (T’s) …from the present outputs ??

15. 3-Bit Synchronous Binary Up Counter Output Count Output Y 2 Output Y 1 Output Y 0 Input Needed T 0 Next Output Y 0 + 0000 1001 2010 3011 4100 5101 6110 7111 0000 101010101101010101 111111111111111111 T0 = ??

16. 3-Bit Synchronous Binary Up Counter Output Count Output Y 2 Output Y 1 Output Y 0 Input Needed T 2 Next Output Y 2 + 0000 1001 2010 3011 4100 5101 6110 7111 0000 000111100000111100 000100010000100010 T2 = ?? (K map??)

17. Experiment 8 Overview P1:Design and Simulate a T flip-flop P2:Design and Simulate a 4-bit counter –using your T flip-flop module (structural design) –additional gates as needed. –Include a more detailed Block Diagram than the “Black-box Diagram” shown for your lab report

18. Required Counter Schematic ?? Show the Port names for your components Label any intermediate signals (matching VHDL) Q1 Q2 Q0 Entity Input/Output Port names should match VHDL code Show any connections of Inputs/Outputs to LEDs / Switches used for testing (Proc. 3)

19. Experiment 8 Overview P1:Design and Simulate a T flip-flop P2:Design and Simulate a 4-bit counter –u–using your T flip-flop module (structural design) –a–additional gates as needed. –I–Include a more detailed Block Diagram than the “Black-box Diagram” shown for your lab report P3:Integrate 4-bit Counter with your BCD-7seg Display design (unchanged if possible) –S–Structural Design –V–Visually confirm your counter is working (No ModelSim) –I–Instructor Sign-off –D–Detailed Block Diagram of your Structural Design P4:Verify your Counter with the Logic Analyzer - You may SKIP this…. …but it will cost you 8 points

20. P1:Design and Simulate a T flip-flop P2:Design and Simulate a 4-bit counter –u–using your T flip-flop module (structural design) –a–additional gates as needed. –I–Include a more detailed schematic than the “Block Diagram” shown for your lab report P3:Integrate 4-bit Counter with your BCD-7seg Display design (unchanged if possible) –S–Structural Design –V–Visually confirm your counter is working (No ModelSim) –I–Instructor Sign-off –D–Detailed Schematic of Structural Design P4:Verify your Counter with the Logic Analyzer

21. Next Week Structural Design Integration of Past Designs into a Digital Alarm System Finite State Machine Design with VHDL Required Preparations: Read Special Lab Instructions –`“Experiment 9A”

22. Next Week 1.Finite State Machine Design with VHDL 2.Structural Design Integration of Past Designs into a Digital Alarm System Required Preparations: VHDL Tutorial on FSM design Read Lab Instructions Prepare a “State Transition Diagram” and “Present State / Next State (PS/NS) Table” for your Alarm System Finite State Machine –Turned in at BEGINNING of Next Week’s Lab Prepare a draft of the Structural Design for the complete Alarm System (assuming a module exists for the Alarm FSM). –Turned in at BEGINNING of Next Week’s Lab