Presentation on theme: "Announcements Assignment 6 due on Friday Project ideas due today"— Presentation transcript:
1 Announcements Assignment 6 due on Friday Project ideas due today Need to try to place orders this week.Your responsibility when ordering parts includes: getting them in time, getting correct part numbers, finding replacements for obsolete parts, and checking availability (no back orders, no large minimum quantities).For chips, you want DIP (dual inline package), not SOICIf using digikey for many parts, make up an order list, and send me the Web ID & Access ID
2 Announcements Joe: Game show Buzzer Trisha & Matt: EMG (?) Jamy: LED cubeJingliang: Piezoelectric chargerEric: Water printer(?)
4 The R-S latchCross-coupled gates form an R-S latch with two stable states (bistable multivibrator)INPUTOUTPUTABA NOR B1SRQQ’S=1, R=0 : Q=1, Q'=0S=0, R=1 : Q=0, Q'=1S=0, R=0 : hold stateS=1, R=1 : unstable
5 One-shot A monostable multivibrator can be very useful produces an output pulse with the correct voltage levels and of adjustable width74121 one-shot (monostable multivibrator) non-retriggerable.Output pulse width is determined by an external RC network
6 One-shotThe is non-retriggerable - it ignores input transitions when the output pulse is HIGHIt is often more useful to use a retriggerable one-shot; e.g. 74LS122For this type of input both behave the sameFor this type:
7 Oscillators Digital circuits also need clocks. We can create a simple "relaxation oscillator" using the Schmitt trigger:v+=vo/2v-=vCThis sets the clock period ( RC)This sets the threshold levelsThis is an astable multivibrator (no stable state)
8 OscillatorsFor lowish frequencies (<1MHz), a cheap and reliable clock can be made with a 555 timer chip.
12 555 TimerVoltage dividerAlternatively, we can set Vcontrol externally:Control VoltageVcontrol = VcontrolVtrig = 1/2 Vcontrol
13 555 Timer Two Comparators: Output a HIGH voltage level when the "+" input is greater than the "-" input.Upper comparator: Threshold input is compared to VcontrolLower comparator: Trigger input is compared to Vtrig.Results are passed to a flipflopVcontrolVtrig
14 555 TimerFlipflop:Stores the information of which comparator last passed it a high voltage.If Threshold>Vcontrol ;S=1Output state is HIGH. Transistor is switched onIf Trigger< Vtrig;R=1Output state is LOWTransistor is switched off.SQVcontrolRVtrig
15 555 Timer: Monostable configuration. Single pulse Initial state: flipflop is "set". Point C is HIGH.Transistor is on - passing capacitor charge to ground.When trigger input at A goes LOW, bottom comparator triggers and E goes HIGH.Flipflop changes state: C goes LOWTransistor is off - capacitor starts charging (B) through RWhen point B reaches 2/3 Vcc, flipflop changes state, transistor is on, capacitor discharges rapidly.Output pulse is just the inverse of CWidth of output pulse = 1.1RC555 Timer: Monostable configuration. Single pulseBDCtrigger inputEAACapacitor voltageBFF outputCDupper comp.Elower comp.
16 555 Timer: Astable configuration In this mode, connect both comparator inputs to the capacitor in order to generate a clock.Charge up through RA+RB, discharge through RBCapacitor charging and discharging times can be controlled by resistor selection, in order to define the clock period and duty cycle
17 555 Timer: Practical limits For reliable performance:The resistors RA and RB must be between 1kΩ and 3MΩThe capacitor C must be greater than 500pFShortest period ~ 510-7, (Max frequency fmax= 2MHz)If RB>>RA, duty cycle ~50% (square wave oscillator)Power supply drift is not a problem - time constant is independent of power supply - only depends upon resistor and capacitor values.Buffer at last stage can provide enough current to drive many TTL loads