Presentation on theme: "Ivan Seskar Rutgers, The State University of New Jersey "— Presentation transcript:
1Cognitive Radio Kit Framework : Experimental Platform for Dynamic Spectrum Research Ivan SeskarRutgers, The State University of New JerseyContact: Ivan Seskar, Associate Directorseskar (at) winlab (dot) rutgers (dot) edu
2Cognitive Radio (CR) platforms Research community already has a variety of platforms for CR researchMicrosoft SoraUSRP2USRPMIT AirblueU. Of ColoradoRICE WARP Platform
3Cognitive Radio platform issues Problems with existing (experimental) platforms: do we wait for Moore’s law to catch up or we need new hardware architectures for CR?“Analog” issues: range (frequency, power), agility, cost, scalability, future proofing“Digital” issues: scalability, power consumption, performance vs. flexibility, cost, future proofingEase of “use” issues: how do we program/control these platforms?Large scale experiments in realistic environmentsNation-wide (experimental) cognitive radio spectrum allocationMultiple testbeds with different objectivesGENI advanced technology demonstrator of cognitive radio networksAddress New Application NeedsSpectrum sensing, vehicular networking
4Spiral II GENI project: CR kit Range of baseband FPGA platforms4 (2) configurable radio modules for phased or smart antenna applications withPhase I: Each module allows two 25 MHz bands from 300 to 6000 MHzPhase II: Each module allows two different 300 MHz bands from 100 to 7500 MHzEach module supports independent full duplex operation.1 usec RF frequency switching timeSwitched antenna diversity for both TX and RX channels.nWide-tuning Digital Radio (WDR) block diagram
5Why CRKIT Framework ?INNOVATION CYCLEFocus on Creativity, not Engineering Complexity :Split Baseband in two domain spaces :Dynamic – Swappable Communication APPs(creative problem)Static - Open-sourced System-on-Chip(complex engineering problem)Focus on APP DevelopmentNOT complete RadioAbstract lower level design complexities from UsersFSoC FeaturesAccess to lower level resources thru APIsVITA radio transport protocol for radio controlNetworking capable nodeSupport up to four dynamic APPsLibrary of Open-sourced Communication APPsStatic Framework utilization level < 15% for V5SX95, even less for newer technologies, for ex. Virtex7 .Transparent to underlying FPGA technology.Can be ported to future HW platforms and newer FPGA technologies.Build Radio :Non trivial effortSubstantial barrier to entryMany engineering man-hours neededRequires cross-disciplinary expertiseLive system runsCRKIT = make real-time and wide-tuning radio a viable solution for large scale experiments.WDR from Radio Technology Solutions
6CRKIT Framework Overview HWPlatformSWPlatformORBITIntegrationWide-tuningRadioFlexibleBasebandEmbeddedHOSTPHYLayer Exp.Exp.ScalabilityFPGA-SoCComm.APPsRadioAPIsOMFBaseband Processor :FPGA-based off-the-shelf boardMultitude of high-speed IOs : GigE, USB, PCIeControl up to 4 full-duplex wideband radiosFPGA-based System-on-Chip (FSoC) implementationWide-tuning Radio (WDR) Module :Wide-tuning range : 100MHz to 7.5GHz36MHz bandwidth50Msps 12-bit ADC, 200Msps 12-bit DAC1us switch between frequencies
7FPGA SoC Overview Three distinct data flows through system: FPGA SoC components :Ethernet Port (static)Gigabit Ethernet rateframe synchronizationframe generation/formattingPacket Processor (static)packet classification/forwardingControl packets -> Processor CoreData packets -> APPMemory management for APP dataIP/VITA packet generation/formattingApplication (dynamic)User specific designs e.g. simple QPSK/QAM, OFDM, FHSS, DSSS…Support up to 4 APPs simultaneouslySwappable APPs, can either reside in RAM or downloadable through Ethernet port.RF Port (static)interfacing to DA/ADRMAP Processor (static)Sub-system interfacing and controlAddress decodingRF SPI ControlProcessor Core (static)32-bit Softcore processorbus interconnectinterfacing to 32MB DRAMinterfacing to 16MB FLASHThree distinct data flows through system:1) APP/Processor Core to outbound ethernet port2) Inbound ethernet port to APP3) Inbound ethernet port to Processor Core
8CRKIT Transport Layers APP domain (dynamic)Framework Domain :Framework domain (static)ETH Layer – Ethernet Physical layer only, no MAC. Only Ethernet frames with Broadcast MAC or matching destination MAC addresses are forwarded to IP layer.IP Layer (Fast Path) –Hardware based implementationOnly a subset of IP and UDP functions.Fast track is reserved for APP data related trafficData IP packets are routed to the fast track based on specific UDP port number.IP Layer (Slow Path) –Software based implementationSupport TCP as this is done in SW e.g. processor core.Slow track is reserved mostly for control related traffic : CRKit hardware configuration (register map access) and RF control.Any IP packets with UDP port number not matching the fast track UDP port number will be routed to the slow track.Note : for Address Resolution Protocol (ARP) the IP layer is bypassed, we parse the packets based on Ethernet frame Ethertype field.VRT Layer –VITA Radio Transport layer, only a subset of VITA standard is supported.VRT layer is optional, bypass this layer if not used.VRT useful to mux multiple radio streams to a single pipe, and demux at the other end.Standardized radio packet types: 1) Data for signal data transmission, could be digitized I/Q samples. 2) Context for control information such as set frequency, power level, bandwidth and so forth.Application Domain :User Specific Layer - since we are in the APP domain, users have their freedom to add any new layers they may wish.Wireless PHY – again user specific implementation.
9Inbound Data Flow PCORE CMD FORMAT Ethertype = 0x0800 - IPv4 0x ARPIf (V==1) thenVITA context packetElsenon-VITA packetuse ethertype field for further parsingEndif;Use CMD_CNT as ACK to MEM_CTL to indicate completion of PCORE data removal from MEM.PortID LookupTableForward ethernet payload if :incoming MAC = dMACincoming MAC = BroadcastAppend Ethertype field (16-bit) to ethernet payloadif (ethertype == IPv4 & Incoming IP == dIP & UDP = ) thenforward UDP payload to VITA Receiverelseforward packet to PCORE
10Inbound Register Map For UDP Port 1000 Traffic (VITA) Registers visible to PCOREFor non-VITA trafficUDP 1001 => P0UDP 1002 => P1UDP 1003 => P2UDP 1004 => P3StreamID lookup(direct-mapped)APP Identifier
11Outbound Data Flow If IP-Flag then IP packet processing. Lookup using PortIDVRT ReceiverLookup using PortIDif V-Flag then Enable VITA formatting
12Outbound Packet Processor RMAP VITA enable flagIP enable flagVITA headerIP headerLookup using PIDData/ContextLookup using PIDStreamID Lookup TableMAC/IP Lookup Table
23ORBIT Integration OPEN TO ORBIT COMMUNITY ! Actual SB6 with two CRKITs ORBIT SB6OPEN TO ORBIT COMMUNITY !
24ConclusionCRKIT = Advanced Radio System enabling experimental research in CR and DSA techniquesPowerful combination of Wideband Radio and Flexible Baseband ProcessingFSoC Static and Dynamic domain spacesAPP development for Creativity and Productivity => MATLAB/SimulinkFramework development for Engineering Complexity => Traditional Hardware design flowORBIT Integration => User Friendliness Experience + Experimentation Scalability
25Future Work Extend APP library : OFDM-based waveform APP Upgrade Static framework to support live loadable APPs from Network :Clock ManagementRun-time ReconfigurationPort Linux to PCOREIntegrate CRKIT fully into ORBIT Management Framework (OMF)Extreme Digital Radio (XDR) : 800MHz BandwidthUpgrade baseband processor board to newer and higher performance FPGA technologies