1. System Block Diagram MemDataIn is the input port AddressOut and WriteDataOut are output ports Reset clears regfile and all registers Ignore memory control signals for now MemoryDatapath MemDataIn AddressOut WriteDataOut clkreset Controller Zero csignals MemWrite, MemRead Opcode Funct

2. Program Execution Only two system inputs, reset and clock Reset zeroes out all registers Sets PC to first memory address After reset the program at location 0 should be executed PC should increment after each instruction (except beq) Memory must contain program at address 0

3. Controller Design Controller zero opcode (IR 31-26) funct (IR 5-0) ALU Control aluOP most control signals ALU control signals Datapath needs new outputs opcode and funct Controller is sequential, ALU Control is combinational Reset and clock signals not shown

4. Main Controller case (opcode) begin 35: cseq_lw(sclk); 43: cseq_sw(sclk); 0: cseq_rtype(sclk); … A big case statement based on the opcode Assume a task for each instruction type Opcodes will be given to you

5. ALU Control case (ALUOp) begin 00: ALUcontr = 010; 10: case (funct) begin 32: ALUcontr = 010; … A big case statement based on ALUOp and funct Assume a task for each instruction type Opcodes and functs will be given to you

6. Testing the CPU Modify the Verilog code of the memory Write a program starting at location 0 Reset the machine Check the results of the program