1. 5.2.06 הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל המעבדה למערכות ספרתיות מהירות High Speed Serial Link Traffic Generator & Analyzer Verification Final Presentation Final Presentation Author : Moshe Porian Supervisor : Boaz Mizrachi

2. Project Goals achieved - High level: Implementation of correct verification method: Implementation of correct verification method:  Get the real design as “black box” with it specification.  Building architecture and micro architecture of your verification design.  Code and simulate your verification design.  Plant the real design in your environment.  Nagging inputs (including random mechanism), follow design outputs, compare with expected results.  Read results and reports if pass/fail with point to the problem.  Building sets of test to cover all optional scenes  Automation of the tests and reports.

3. Building a Generator Checker Unit Building a Generator Checker Unit Configure set of parameters and testing Configure set of parameters and testing Emulate the connection from the PC to the Generator Emulate the connection from the PC to the Generator Easy collect results by designing Compare Unit which report to log out file simple messages that direct the user to the bugs. Easy collect results by designing Compare Unit which report to log out file simple messages that direct the user to the bugs. Generating different packets with different errors plants on it in purpose to check the Analyzer functioning. Generating different packets with different errors plants on it in purpose to check the Analyzer functioning. Building a Reference Model of the Analyzer for providing a number of indications Building a Reference Model of the Analyzer for providing a number of indications Project Goals achieved - Low level:

4. PPC EMU GENERATOR TGA Verification – Block Diagram Script File ANALYZER GENERATOR CHECKER Reference Model of the Analyzer Compare & Analyze Unit Log out File Config File RocketIO EMU Packet Generator For the Analyzer

5. PPC EMULATION  The Script syntax is as follows:  Read (, )  Write (,, )  Where :  = ‘P’ – Generator BRAM ‘T’ – Analyzer BRAM ‘T’ – Analyzer BRAM  = 32 bits: xxxxxxxxh

6. PPC EMU I/O Interface Every clock cycle the PPC EMU generate data & address outputs according to the instructions from script file. Every clock cycle the PPC EMU generate data & address outputs according to the instructions from script file.

7. PGP BRAM EMULATION

8. PGP BRAM EMU I/O Interface

9. PGP BRAM EMU functionality  The Generator address pattern is: x”ffff00##”  Every address is a multiple of 4 2^8)/4= 64  (2^8)/4= 64 Address space range of the PGP BRAM  Address space range of the PGP BRAM EMU is [0..63] EMU is [0..63]

10. Generator Checker Define registers and counters which survey the outputs of the GENERATOR Define registers and counters which survey the outputs of the GENERATOR verify that the results are appropriate to the instructions from the PPC EMULATION. verify that the results are appropriate to the instructions from the PPC EMULATION. Generator verification: Generator verification: Number of packets,Packet length,Header length, Stamp length,Burst size,Inter Burst Gap Inter Packet Gap,Header Data,Stamp Data, Start/End Padding Data

11. GEN CHECK I/O Interface

12. Packet Structure

13. GEN CHECK State Machine STAMP_DATAGAP_DATA END_TEST WAIT4SOP HEADER_DATA INIT_CONFG WAIT4POLLING INIT CNT LEN & ERR Ram data(0)='1' INIT CONFG REGS START='1' IDLE SOP ASSUME HEADER LEN CORRECT DATA = HEADER DATA = STAMP EOP IDLE SOP FINISH='1'

14. Regression test  Demonstrating different high speed serial links design considerations and there impact on the system performance.  Set of scripts files.  A TCL script (do. file) manage the passage between the different scripts files.  The results of each test are reported to a logout file.  An EXE file cross all over those files and search for an error. If there is any error it report in which logout file the test was failed (simple messages that direct the user to the bugs).

15. RocketIO Emulation Configuration of the Packet Generator for the Analyzer. Configuration of the Packet Generator for the Analyzer. The traffic data include: rxdata - 32 bits of data, status signals which indicate the error detection by the receiver. The traffic data include: rxdata - 32 bits of data, status signals which indicate the error detection by the receiver. Plant errors in the data to the Analyzer in purpose to verify Analyzer design. Plant errors in the data to the Analyzer in purpose to verify Analyzer design.

16. Randomization Mechanism Randomization of: Randomization of:  Packet characterization: Packet length, Inter Packet Gap, Inter Burst Gap, Stamp length, and Burst size.  Error plant: CRC error, recovery clock timing, disparity error, not in table error. Random number in range [min.. max] as depend on the randomization seed. Random number in range [min.. max] as depend on the randomization seed. For the packet characterization: as depend on the state machine the relevant counter is loaded. For the packet characterization: as depend on the state machine the relevant counter is loaded. For the error plant: the max and min are 100 and 0, so, a number in this range is randomized. A probability number from the Config file is compared with this value at the relevant time. For the error plant: the max and min are 100 and 0, so, a number in this range is randomized. A probability number from the Config file is compared with this value at the relevant time.

17. Reference Model of the Analyzer Analyzes the incoming test-traffic and provides the results to the PPC. Analyzes the incoming test-traffic and provides the results to the PPC. Each packet is analyzed for potential error – if detect any error during the packet the bad packet is stored. Each packet is analyzed for potential error – if detect any error during the packet the bad packet is stored. Supply indication : number of damaged/undamaged packets during the test, status flags of the bad packet which direct the user to the cause of the error, counters of specific errors, like: CRC, los of sync, K-char, not in table, number of recovery clock, transmission delay. Supply indication : number of damaged/undamaged packets during the test, status flags of the bad packet which direct the user to the cause of the error, counters of specific errors, like: CRC, los of sync, K-char, not in table, number of recovery clock, transmission delay. The user can compare the analyze results of the Ref model with the real results from the Analyzer. The user can compare the analyze results of the Ref model with the real results from the Analyzer.

18. END_ST End_test = ‘1’ WAIT4SOP Sop_snifer = ‘1’ Time_cnt_en = ‘1’ PACKET_DATA Packet_rec = ‘1’ Time_cnt_en = ‘1’ IDLE_ST INIT: address, address of last error, arrays of pointers and error status START='1' SOP_DATA FINISH = ‘1’ EOP_DATA FINISH = ‘1’ Sop_snifer Packet_rec End_pack_det Only in the first clock: If err_det = ‘1’ then Load to add_last_err current address Update – error status array & pointers array If this is the first clock in this sate: Load to current address the add_last_err Otherwise: increment address In addition: data out = data in Spill the rest of the data to the TSS BRAM – array of pointers, array of status error, time delay, counters of error

19. Project Summary Implementation of correct verification method Implementation of correct verification method  Separation between the verification designer with the RTL designer  Determine concept of the verification through building architecture and micro architecture.  Coding and simulating.  Building sets of test to cover all optional scenes  Automation of the tests and reports.

20. Project Conclusions The Generator function as required. The Generator function as required. Miss match in the address space between the code and the specification document. Miss match in the address space between the code and the specification document. Continue the project: the Analyzer shall be checked… Continue the project: the Analyzer shall be checked… Instead of VHDL use System Verilog Language Instead of VHDL use System Verilog Language  Assertion  Random generation  Functional Coverage