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A COMPARATIVE STUDY OF MULTIPLY ACCCUMULATE IMPLEMENTATIONS ON FPGAS Using Distributed Arithmetic and Residue Number System

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Project Scope To compare the implementation efficiencies (area times delay) of Distributed Arithmetic (DA), RNS and DA- RNS based parallel multiply accumulate architectures on FPGAs

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Background and Context FPGAs increasingly used for DSP computations FPGAs have potential for parallelism FPGAs architecture exploitation (LUT based) Novel MAC architectures especially suitable for FPGAs

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Some More Background In DSP MACs use constant coefficient (Fixed Multiplicand) Full Multiplier Implementation Not Required Not All Multiplier Architecture Efficient for FPGAs

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Motivation Distributed Arithmetic and Residue Arithmetic techniques are LUT based techniques Explore the “synergy” between FPGA architecture and above mentioned techniques

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Distributed Arithmetic Overview

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Basic Serial Architecture

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Residue Arithmetic Overview (z1, z2,..., zn) = ( x1, x2, …, xn) (y1,y2, …, yn) zi = (xi yi) mod mi denotes any of the modulo operations of addition, subtraction or multiplication

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Modulo Adder

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Modulo Constant Multiplier Due to the small sizes of residues and a constant multiplicand, a direct LUT based implementation is very efficient 4-bit Constant Modulo Multiplier A0 A1 A2 A3 X[3:0] 5-bit Constant Modulo Multiplier A0 A1 A2 A3 X[4:0] A4

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RNS MAC Architecture

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Conversion Issues in RNS Binary to RNS and RNS to Binary Conversion are significant overheads Binary to RNS relatively simple RNS to Binary Using a Direct CRT Implementation Requires Modulo M adders

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Forward Conversion

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Reverse Conversion

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DA-RNS Coupling

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Scaling Accumulator Design

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DA 8-bits 8 Taps 12-bits Coefficients Implementation

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Critical Path Results Source: PSC8_0_PSC_0/I_Q7 (FF) Destination: SACC24_REG2/I_Q3 (FF) Data Path: PSC8_0_PSC_0/I_Q7 to SACC24_REG2/I_Q3e)

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