1. IUCEE Workshop presentation-YVJoshi VLSI Signal Processing Y. V. Joshi SGGS Institute of Engineering and Technology, Nanded

2. IUCEE Workshop presentation-YVJoshi Introduction Efficient implementation of signal processing algorithms required for real time signal processing Many ways –Working at architectural level –Implementation level Using Digital Signal Processors Using FPGAs Using Full custom design

3. IUCEE Workshop presentation-YVJoshi Typical DSP algorithms Simple –Convolution/Correlation –Transformations- FFT/DCT/Wavelet –Digital filtering –Filter banks Complex –Neuro Computing –Computer Vision –Artificial organ development etc

4. IUCEE Workshop presentation-YVJoshi Applications MP3 players Mobiles Embedded systems (automobiles, aircraft, satellite etc) Robots Projection systems Biomedical/Life support systems Communication systems- Software defined radios, etc

5. IUCEE Workshop presentation-YVJoshi Architectural level Techniques of reducing the critical path –Pipelining and Parallel Processing –Retiming –Unfolding –Folding Dependent on optimization in data flow graphs

6. IUCEE Workshop presentation-YVJoshi Implementation level- DS Processors Selection of DSP based on application demand –Analog Devices DSP –TI DSP –Motorala DSP Selection of Tools/Hardware platforms Development of algorithms on DSP

7. IUCEE Workshop presentation-YVJoshi Implementation level- FPGA Selection of FPGA based on application demand –Xilinx –Alterra Selection of Tools/Hardware platforms Development of algorithms for FPGA

8. IUCEE Workshop presentation-YVJoshi Implementation level- Full Custom VLSI based Selection of EDA tool based on application demand –Cadence/Tanner/Laker Selection of Design methodology Development of layouts (LVS/DRC clean) Chip mfg.

9. IUCEE Workshop presentation-YVJoshi Resources Basic units –Adder –Multiplier and –A delay Structures used in Signal processing –Simple Direct form/Transpose form –Cascade/Parallel –Digital two pair/Lattice –Single multiplier per order structure –Derived structures (low sensitivity to coefficient quantisation)

10. IUCEE Workshop presentation-YVJoshi Example A second order notch filter Using allpass structure

11. IUCEE Workshop presentation-YVJoshi Example (Contd…) With values of With being the notch frequency and being the rejection bandwidth implementation with only two multipliers with minimum critical path

12. IUCEE Workshop presentation-YVJoshi Thanks Contact : Y. V. Joshi Yashwant.joshi@gmail.com