1. 18-743 Project Report II RIPE: A Rapid Implication- based Power Estimator Sunil Motaparti, Gaurav Bhatia

2. OUTLINE Problem to Solve Problem to Solve Motivation Motivation Approach Approach Previous Milestone Previous Milestone Current Milestone Current Milestone Milestone Schedule Milestone Schedule

3. PROBLEM TO SOLVE Gate Level Power Estimation Gate Level Power Estimation Computing Average switching activity of a circuit gives a somewhat accurate estimation of power consumption Computing Average switching activity of a circuit gives a somewhat accurate estimation of power consumption Consideration of spatio-temporal correlations yield more accurate estimations of the average switching activity Consideration of spatio-temporal correlations yield more accurate estimations of the average switching activity Done using Markov chains which compute step- transition probabilities (as discussed in lecture) Done using Markov chains which compute step- transition probabilities (as discussed in lecture)

4. MOTIVATION Some of the Early work has not dealt with reconvergent fanout Some of the Early work has not dealt with reconvergent fanout More recent work that deals with the above has involved using OBDD’s which are computation intensive and slow More recent work that deals with the above has involved using OBDD’s which are computation intensive and slow Most of the approaches have not been line independent and hence an algorithm which can reduce this dependency is desirable Most of the approaches have not been line independent and hence an algorithm which can reduce this dependency is desirable

5. APPROACH Static Learning (also called Static Logic Implication) can be used Static Learning (also called Static Logic Implication) can be used Find implications of setting a line l to a particular value v Find implications of setting a line l to a particular value v Direct Implications Direct Implications Forward / Backward Simulation Forward / Backward Simulation Indirect Implications Indirect Implications Contrapositive Law Contrapositive Law Extended Backward Implication Extended Backward Implication Iterative Iterative Implemented using set operations Implemented using set operations Implicitly captures the reconvergent fanout structures in the circuit Implicitly captures the reconvergent fanout structures in the circuit

6. APPROACH (contd.) Computing Step Transition Probabilities Computing Step Transition Probabilities Find Crucial Nodes Find Crucial Nodes Sets of Nodes through which paths from primary inputs to lines have to pass through Sets of Nodes through which paths from primary inputs to lines have to pass through Dominators Dominators Min-Cut Min-Cut Limit size to 5-6 Limit size to 5-6 For a set of n crucial nodes, we have 2 n combinations of values for current clock cycle and 2 n combinations of values for next clock cycle For a set of n crucial nodes, we have 2 n combinations of values for current clock cycle and 2 n combinations of values for next clock cycle We have 2 2n pairs of distinct combinations of values We have 2 2n pairs of distinct combinations of values For each pair, we update the transition counts on each line that is present in the implication sets of the current and next combinations by doing set union and set intersection operations For each pair, we update the transition counts on each line that is present in the implication sets of the current and next combinations by doing set union and set intersection operations we compute step transition probability using the formula:- we compute step transition probability using the formula:- stp(x) = (# of times x switched for 2 2n pairs) / 2 2n Mostly Line Independent Mostly Line Independent For nodes that were not covered by any set of crucial nodes, we compute the step transition probabilities one by one For nodes that were not covered by any set of crucial nodes, we compute the step transition probabilities one by one

7. PREVIOUS MILESTONE Finished building event-driven simulator Finished building event-driven simulator Finished Parser Finished Parser Reads benchmarks in structural Verilog and ISCAS89 formats Reads benchmarks in structural Verilog and ISCAS89 formats Implemented certain parts of implication engine (fully tested and debugged) Implemented certain parts of implication engine (fully tested and debugged) Built Forward Implication part Built Forward Implication part Built Transitive Implication part Built Transitive Implication part Finished pseudo-code for the rest of the engine Finished pseudo-code for the rest of the engine

8. CURRENT MILESTONE Finished implementation and testing of the full implication engine Finished implementation and testing of the full implication engine Implemented all types of implications discussed Implemented all types of implications discussed Tested on various benchmarks such as c17, c432, c5315, c7552 Tested on various benchmarks such as c17, c432, c5315, c7552 Execution times for finding implications are usually low with the execution time for the largest circuit being 80.39s on a 750Mhz machine. Execution times for finding implications are usually low with the execution time for the largest circuit being 80.39s on a 750Mhz machine. Currently conducting experiments to get an approximate size of the crucial node computation required Currently conducting experiments to get an approximate size of the crucial node computation required Will start working on crucial node computation implementation after obtaining results Will start working on crucial node computation implementation after obtaining results

9. PROBLEMS SO FAR Parser assumption Parser assumption Parser assumes that a particular input to a gate in a netlist has been instantiated or described before its first use Parser assumes that a particular input to a gate in a netlist has been instantiated or described before its first use Obtained utility to convert benchmarks to adhere to the above assumption, have to make it adapt to the structural verilog format Obtained utility to convert benchmarks to adhere to the above assumption, have to make it adapt to the structural verilog format

10. MILESTONES 1 st Report 1 st Report Build event-driven simulator and various parts of the implication engine Build event-driven simulator and various parts of the implication engine 2 nd Report 2 nd Report Finish building implication engine Finish building implication engine 3 rd Report 3 rd Report Implement Crucial-node computation and finish complete implementation Implement Crucial-node computation and finish complete implementation Final Report Final Report Optimizations (if above milestones are met) Optimizations (if above milestones are met)

11. Questions ?