1. ELEN 468 Lecture 231 ELEN 468 Advanced Logic Design Lecture 23 Testing

2. ELEN 468 Lecture 232 Verification vs. Testing Verifies correctness of design Performed by simulation, hardware emulation, or formal methods Performed prior to manufacturing Verifies correctness of manufactured hardware Two-part process: 1. Test generation: software process executed once during design 2. Test application: electrical tests applied to hardware Test application performed on every manufactured device

3. ELEN 468 Lecture 233 Why Do We Need Testing? Properly designed chip may fail in field Transient failures – under heating, radiation … Intermittent failures – random, finite duration Permanent failures Manufacturing defects Wafer defects Contaminated atmosphere in clean room, dust … Impure processing gasses, water, chemicals … Photomask misalignment

4. ELEN 468 Lecture 234 Testing Levels and Implied Cost Wafer: 0.01 – 0.1 Packaged-chip: 0.1 – 1 Board: 1 – 10 System: 10 – 100 Field: 100 – 1000

5. ELEN 468 Lecture 235 Types of Defects Wire shorts Discontinuous wires, may due to stress or peeling High resistance vias Gate to source/drain junction short Threshold voltage change

6. ELEN 468 Lecture 236 Fault Models Why model faults? I/O function tests inadequate, real defects too numerous and often not analyzable A fault model  Identifies targets for testing  Makes analysis possible Common fault models Transistor open and short faults Single stuck-at faults

7. ELEN 468 Lecture 237 Single Stuck-at Fault Three properties define a single stuck-at fault Only one line is faulty The faulty line is permanently set to 0 or 1 The fault can be at an input or output of a gate Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults a b c d e f 1 0 g h i 1 s-a-0 j k z 0(1) 1(0) 1 Test vector for h s-a-0 fault Good circuit value Faulty circuit value

8. ELEN 468 Lecture 238 Fault Equivalence and Collapsing Fault equivalence: Two faults f1 and f2 are equivalent if all tests that detect f1 also detect f2 Fault collapsing: All single faults of a logic circuit can be divided into disjoint equivalence subsets, where all faults in a subset are mutually equivalent.

9. ELEN 468 Lecture 239 Equivalence Rules sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 AND NAND OR NOR WIRE NOT FANOUT

10. ELEN 468 Lecture 2310 Checkpoints Primary inputs and fanout branches of a combinational circuit are called checkpoints Checkpoint theorem: A test set that detects all single (multiple) stuck-at faults on all checkpoints of a combinational circuit, also detects all single (multiple) stuck-at faults in that circuit. Total fault sites = 16 Checkpoints ( ) = 10

11. ELEN 468 Lecture 2311 Transistor (Switch) Faults MOS transistor is considered an ideal switch and two types of faults are modeled: Stuck-open -- a single transistor is permanently stuck in the open state Stuck-short -- a single transistor is permanently shorted irrespective of its gate voltage Detection of a stuck-open fault requires two vectors Detection of a stuck-short fault requires the measurement of quiescent current (I DDQ )

12. ELEN 468 Lecture 2312 Stuck-Open Example A two-vector stuck-open test can be constructed by ordering two stuck-at tests A two-vector stuck-open test can be constructed by ordering two stuck-at tests A B V DD C PMOS NMOS Stuck-open 1010 0000 01(Z) Good circuit states Faulty circuit states Vector 1: test for A s-a-0 (Initialization vector) Vector 2: (test for A s-a-1)

13. ELEN 468 Lecture 2313 Stuck-Short Example A B V DD C Stuck-short 1010 0 (X) Good circuit state Faulty circuit state Test vector for A s-a-0 I DDQ path in faulty circuit

14. ELEN 468 Lecture 2314 Testing Techniques I DDQ test – detect short circuit current Test pattern generation and verify output

15. ELEN 468 Lecture 2315 Test Pattern for Stuck-At Faults a b c a b c SA1 Y good = a●b●c Y a-SA1 = b●c Test pattern: {a,b,c} = 011 No need to enumerate all input combinations to detect a fault

16. ELEN 468 Lecture 2316 Path Justification and Sensitization ‘1’ Test SA0 Justification Sensitization

17. ELEN 468 Lecture 2317 Functional ATPG – generate complete set of tests for circuit input- output combinations 129 inputs, 65 outputs: 2 129 = 680,564,733,841,876,926,926,749, 214,863,536,422,912 patterns Using 1 GHz ATE, would take 2.15 x 10 22 years Structural test: No redundant adder hardware, 64 bit slices Each with 27 faults (using fault equivalence) At most 64 x 27 = 1728 faults (tests) Takes 0.000001728 s on 1 GHz ATE Designer gives small set of functional tests – augment with structural tests to boost coverage to 98 + % Automatic Test Pattern Generation (ATPG)

18. ELEN 468 Lecture 2318 D-Logic D 1 in good 0 in fault D’ 0 in good 1 in fault X – don’t care InOut 01 10 XX DD’ D Inverter

19. ELEN 468 Lecture 2319 D-Algorithm ‘1’ Test SA0 = trace back input to enable D Monitor output in D logic

20. ELEN 468 Lecture 2320 Algorithm D-ALG PODEM FAN TOPS SOCRATES Waicukauski et al. EST TRAN Recursive learning Tafertshofer et al. Est. speedup over D-ALG (normalized to D-ALG time) 1 7 23 292 1574 ATPG System 2189 ATPG System 8765 ATPG System 3005 ATPG System 485 25057 Year 1966 1981 1983 1987 1988 1990 1991 1993 1995 1997 Algorithm Speedups

21. ELEN 468 Lecture 2321 Fault Simulation Fault simulation Problem Given  A circuit  A sequence of test vectors  A fault model Determine  Fault coverage - fraction (or percentage) of modeled faults detected by test vectors  Set of undetected faults Motivation  Determine test quality and in turn product quality  Find undetected fault targets to improve tests

22. ELEN 468 Lecture 2322 Fault Coverage and Defect Level W = 1 – Y (1-T) W: probability of shipping a defective part Y: manufacturing yield T: fault coverage

23. ELEN 468 Lecture 2323 Fault Simulator in a VLSI Design Process Verified design netlist Verification input stimuli Fault simulatorTest vectors Modeled fault list Test generator Test compactor Fault coverage ? Remove tested faults Delete vectors Add vectors Low Adequate Stop

24. ELEN 468 Lecture 2324 Fault Simulation Scenario Mostly single stuck-at faults Sometimes stuck-open, transition, and path-delay faults Equivalence fault collapsing of single stuck-at faults Fault-dropping -- a fault once detected is dropped from consideration as more vectors are simulated; fault- dropping may be suppressed for diagnosis Fault sampling -- a random sample of faults is simulated when the circuit is large

25. ELEN 468 Lecture 2325 Fault Simulation Algorithms Serial Parallel Concurrent Probabilistic

26. ELEN 468 Lecture 2326 Serial Algorithm Algorithm: Simulate fault-free circuit and save responses. Repeat following steps for each fault: Modify netlist by injecting one fault Simulate modified netlist, vector by vector, comparing responses with saved responses If response differs, report fault detection and suspend simulation of remaining vectors Advantages: Easy to implement, less memory Most faults, including analog faults, can be simulated Disadvantage: Much repeated computation, CPU time prohibitive for VLSI circuits

27. ELEN 468 Lecture 2327 Parallel Fault Simulation Best with two-states (0,1) Exploits inherent bit-parallelism of logic operations on computer words Multi-pass simulation: each pass simulates w-1 new faults, where w is the machine word length Speed up over serial method ~ w-1 Not suitable for circuits with timing- critical and non-Boolean logic

28. ELEN 468 Lecture 2328 Parallel Fault Simulation Example a b c d e f g 1 1 1 1 0 1 0 0 0 1 0 1 s-a-1 s-a-0 0 0 1 c s-a-0 detected Bit 0: fault-free circuit Bit 1: circuit with c s-a-0 Bit 2: circuit with f s-a-1

29. ELEN 468 Lecture 2329 Concurrent Fault Simulation Event-driven simulation of fault-free circuit Only note those parts of the faulty circuit that differ in signal states from the fault-free circuit A list per gate containing copies of the gate from all faulty circuits in which this gate differs List element contains fault ID, gate input and output values Faster than parallel simulation Uses most memory

30. ELEN 468 Lecture 2330 Concurrent Fault Simulation Example a b c d e f g 1 1 1 0 1 1 1 1 1 0 1 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 0 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 a0a0 b0b0 c0c0 e0e0 a0a0 b0b0 b0b0 c0c0 e0e0 d0d0 d0d0 g0g0 f1f1 f1f1

31. ELEN 468 Lecture 2331 Probabilistic Fault Simulation Identify test vectors with high toggle coverage Use them as basis for test vectors Correlation: toggle coverage  fault coverage Toggle tests are simpler

32. ELEN 468 Lecture 2332 Fault Sampling A randomly selected subset (sample) of faults is simulated Measured coverage in the sample is used to estimate fault coverage in the entire circuit. Advantage: saving in computing resources (CPU time and memory) Disadvantage: limited data on undetected faults - hard to identify location of coverage problems

33. ELEN 468 Lecture 2333 Delay Fault Testing Half open circuit Half short circuit Functionality is not affected Timing performance is degraded