1. Students: Shalev Dabran Eran Papir Supervisor: Mony Orbach In association with: Spring 2005 Electrical Engineering Laboratory

2. What is CRC  When we transmit message we want to be sure that the message that was received in the destination is the same one that we sent.  We add to the transmitted message an overhead data for checking it on the received side.  The overhead data called CRC - Cyclic Redundancy Checking.  CRC are used for error detection in communication systems.

3. CRC  We can add parity bit.  More complex CRC add us more information of a possible errors.  When we get a message we calculate the CRC of the received message and compare It to the CRC that was sent.

4. Project Goals Developing a 16bit CRC-GENRATOR for the Rocket I/O experiment using to the Virtex II-pro PPC To PC Packet Generation Patterns PLB Test Status Storage Traffic Generator Traffic Analyzer Rocket I/O Transceiver BRAM 1 BRAM 2 CRC Generator CRC Analyzer

5. specifications On the transmitted side  We get double word stream of data with start_of_data packet and end_of_data packet.  We add a CRC word to the end_of_data packet. On the received side:  Compare the calculated CRC & the received CRC.

6. Properties Data rate – up to 2.5 Gbits /sec. Data width - 32 bits / cycle. Data length is unlimited.

7. Integration transmit Rocket I/O Transceiver CRC Generator Traffic Generator DATA Control DATA Control Data

8. Integration received Rocket I/O Transceiver CRC Analyzer Traffic Analyzer DATA Control DATA Control Data

9. Functional description (8 bit)

10. Extending 8 bit solution to 32 bit DATA D31 D30 D0 ……………………………… D31 CRC=D0 + + D31

11. Polynomial T= matrix of the polynomial Calculating the next level

12. Calculating the CRC M=matrix of polynomial P=CRC degree.

13. The CRC

14. Tests  CRC test – by known vector.  Changing Polynomial.  Integrating in the complete system.  Maximal rate test.  Bypass test.

15. Substitute  Serial CRC.  8, 32 parallel CRC.

16. Schedule  3 weeks – finishing CRC VHDL & simulation.(29.5 – 16.6).  2 weeks – System Implementation. (19.6-30.6).  Exams period.(30.6-27.7).  4 weeks – integration. (27.7 - 23.8).  3 weeks – Tests. (24.8 -13.9).  4 weeks – documentation. (14.9-12.10).

17. THE END

18. CRC block Interface CRC generator Data In Char Isk in Table Accessbypass Data Out Char Isk out

19. HDL Designer Block Diagram For Transmitter

20. HDL Designer Block Diagram For Receiver