1. Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 1 ELEC 5200-001/6200-001 Computer Architecture and Design Spring 2015 Microprogramming (Appendix D) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu

2. Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 2 Alternatives for Control Unit (CU) Hard-wired (hardware) –Random logic, programmable logic array (PLA), or ROM –Fast –Inflexible Firmware –Microprogrammed or microcoded CU –Control implemented like a computer (microcomputer) MicroinstructionsMicroprogram –Flexible Software-like changes to instruction set possible Completely different instruction sets can be emulated –Speed limited by microcomputer memory

3. 26-31 to Control FSM Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 3 Multicycle Datapath PC Instr. reg. (IR) Mem. Data (MDR) ALUOut Reg. A Reg. B Reg. ALU Register file Memory Addr. Data 4 Sign extend Shift left 2 ALU control 0-5 0-15 16-20 21-25 IorD MemtoReg ALUOp ALUSrcBALUSrcA RegDst IRWrite RegWrite MemWrite MemRead Shift left 2 0-25 28-31 PCSource PCWrite etc. 11-15

4. Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 4 Multicycle Control FSM Instr. decode/reg. fetch/branch addr. ALU operation Write PC on branch condition Write memory data Write jump addr. to PC Write register Read memory data Instr. fetch/ adv. PC Compute memory addr. Write register lw or sw lw sw R B J Start State 0 1 23 45 6 7 8 9 Inputs: 6 opcode bits Outputs: 16 control signals

5. Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 5 States and Outputs Suppose 10 states are encoded 0000 through 1001. State code completely determines 16 control signals (Moore machine). States 0 (0000), 3 (0011) and 6 (0110) Next state ← present state + 1 State 1 (0001) – opcode determines next state State 2 (0010) for lw or sw State 6 (0110) for R-type of instruction State 8 (1000) for branch instruction State 9 (1001) for jump instruction State 2 (0010) – opcode determines next state State 3 (0011) for lw State 5 (0101) for sw States 4 (0100), 5 (0101), 7 (0111), 8 (1000) and 9 (1001) – next state is unconditionally 0 (0000)

6. Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 6 A Program-Like Implementation Instr. decode/reg. fetch/branch addr. ALU operation Read memory data Instr. fetch/ adv. PC lw or sw lw sw R B J Start State 0000 0001 0010 0011 0100 0101 0110 0111 10001001 Inputs: 6 opcode bits Outputs: 16 control signals Compute memory addr. Write jump addr. to PC Write register Write memory data Write register Write PC on branch condition

7. Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 7 Implementing with ROM Control PLA or ROM 16 words Four flip-flops 16 control signals PLA input or ROM address 6-bit opcode State sequencer Select one of 4 ways 16 2 4 6

8. Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 8 ROM and State Sequencer Control ROM Sixteen 18-bit words 4-bit address 4-bit state flip-flops 16 2 Control signals to datapath 4 4 0001 MUX 11 10 01 00 0000 AddrCtl go to 00 st. 0 11 st. + 1 01 st. 2,6,8,9 10 st. 3,5 Dispatch ROM 2Dispatch ROM 1 Adder 6 6-bit Opcode from IR Address Advance state 4 ROM Address sw, lw, R, B or J sw or lw

9. Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 9 Dispatch ROM Contents Dispatch ROM 1 InstructionAddress(Opcode)Content lw1000110010 sw1010110010 R0000000110 B0001001000 J0000101001 Each dispatch ROM has sixty-four 4-bit words Address is 6-bit opcode Content is next state (4-bits) Dispatch ROM 2 InstructionAddress(Opcode)Content lw1000110011 sw1010110101

10. Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 10 Control ROM Contents Control ROM has sixteen 18-bit words: – bits 0-1, AddrCtl to control mux – bits 2-17, sixteen control signals for datapath Address is 4-bit state of control machine Addr. bits 17-2 bits 17-2 bits 1-0 bits 1-0 0000100101000000100011 0001000000000001100001 0010000000000001010010 0011001100000000000011 0100000000100000001000 0101001010000000000000 0110000000000100010011 0111000000000000001100 1000010000001010010000 1001100000010000000000

11. Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 11 Microprogram: Basic Idea The control unit in a computer generates an output (sequence of control signals) for each instruction. Suppose we break down each instruction into a series of smaller operations (microinstructions), such as, fetch, decode, etc. Then, implement the control unit as a small computer (within the computer) that executes a sequence of microinstructions (microprogram) for each instruction. M. V. Wilkes, “The Best Way to Design an Automatic Calculating Machine,” Report of Manchester University Computer Inaugural Conference, pp. 16-18, 1951. Reprinted in E. E. Swartzlander (editor), Computer Design Development: Principal Papers, pp. 266-270, Rochelle Park, NJ: Hayden, 1976.

12. Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 12 Maurice V. Wilkes Born June 26, 1913, Staffordshire, UK, died November 29, 2010 1967 Turing Award citation: Professor Wilkes Is best known as the builder and designer of the EDSAC, the first computer with an internally stored program. Built in 1949, the EDSAC used a mercury delay line memory. He is also known as the author, with Wheeler and Gill, of a volume on “Preparation of Programs for Electronic Digital Computers” in 1951, in which program libraries were effectively introduced.

13. Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 13 Microcoded Control Unit Sixteen 18-bit words 4-bit address 4-bit state flip-flops 16 2 Control signals to datapath 4 4 0001 MUX 11 10 01 00 0000 AddrCtl Dispatch ROM 2Dispatch ROM 1 Adder 6 Opcode from IR Address Microcode memory μPC Address select logic Microcode word Sequencing field lw or sw sw, lw, R, B or J ROM address

14. Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 14 Implementing the Idea Use a memory type implementation for control unit. Create a software infrastructure to automatically translate instructions into memory data (microcode): Microinstructions – define a machine language in which instructions can be described Microprogram – an instruction described as a sequence of microinstructions Microassembler – converts microprogram to (binary) microcode Is there a micro-compiler?

15. Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 15 Microprogramming A microinstruction set is defined. To program the control of a computer for an instruction set, a programmer writes a microprogram for each machine instruction. Each micrprogram is converted into microcode, specific to the datapath hardware, by a microassembler and the entire microcode is loaded in the microcode memory of the control unit (CU).

16. Breaking Up MIPS Instructions R-type instruction: FetchDecode ALU operation Write register lw:FetchDecode Memory address computation Read memory Write register Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 16

17. Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 17 Microinstructions for MIPS ISA Fetchfetch instruction Decodedecode instruction, read registers, calculate branch address RegWrwrite register LWSW1compute memory address LW2memory read SW2memory write R1register type execution BEQ1branch execution JUMP1jump execution

18. Let’s Construct MIPS Instructions R-type instruction: FetchDecodeR1RegWrlw:FetchDecodeLWSW1LW2RegWr sw: Fetch Decode LWSW1 SW2Branch: Fetch Decode BEQ1Jump: Fetch Decode JUMP1 Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 18

19. Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 19 Microinstruction Format Just one instruction with seven arguments A label or name for control state(s), e.g., Fetch, MEM1, etc. Seven arguments and their possible values: –ALU controladd, subtract or funct. code# result to ALUOut –SRC1PC or A –SRC2B, 4, extend or extend-shift –Reg. controlRead# read two reg. specified by IR into A and B Write ALU# write ALUOut to register file Write MDR# register file ← MDR –MemoryRead PC# IR ← M[ PC ] Read ALU# MDR ← M[ ALUOut ] Write ALU# M[ ALUOut ] ← B –PCWriteALU# write PC from ALU ALU cond.# If zero = 1, PC ← ALUOut Jump addr.# PC ← jump address – –SequencingSeq# choose next μInst. Sequentially fetch# go to first μInst. to begin new instr. Dispatch i# use Dispatch ROM i, i = 1 or 2

20. Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 20 Sequencing Illustrated Instr. decode/reg. fetch/branch addr. ALU operation Write PC on branch condition Write memory data Write jump addr. to PC Write register Read memory data Instr. fetch/ adv. PC Compute memory addr. Write register lw R1BEQ1 JUMP1 State 0 1 23 45 6 7 8 9 Sequencing = seq Dispatch 1 Dispatch 2 seq Fetch LW2 SW2 LWSW1

21. Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 21 Microinstruction Arguments Argument Value Value μCode value Action ALU Ctrl Add ALUOp = 00 ALU adds Subt ALUOp = 01 ALU subtracts for beq Funct code ALUOp = 10 ALU executes R-type instruction SRC1PC ALUSrcA = 0 PC is first ALU input A ALUSrcA = 1 Reg A is first ALU input SRC2B ALUSrcB = 00 Reg B is second ALU input 4 ALUSrcB = 01 Constant 4 is second ALU input Extend ALUSrcB = 10 Sign extension unit is second ALU input Extshft ALUSrcB = 11 2-bit shift unit is second ALU input

22. Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 22 Microinstruction Arguments (Cont.) ArgumentValue μCode value Action Reg. Ctrl Read Load A and B from Register file Write ALU RegWrite = 1 RegDst = 1 MemtoReg = 0 An IR-specified register in Register file is written from ALUOut Write MDR RegWrite = 1 RegDst = 0 MemtoReg = 1 An IR-specified register in Register file is written from MDR Memory Read PC MemRead = 1 IorD = 0 IRWrite = 1 IR ← M[ PC ] MDR ← M[ PC ] Read ALU MemRead = 1 IorD = 1 MDR ← M[ ALUOut ] Write ALU MemWrite = 1 IorD = 1 M[ ALUOut ] ← B

23. Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 23 Microinstruction Arguments (Cont.) Field μInstr. value μCode value Action PC Write Ctrl ALU PCSource = 00 PCWrite = 1 Register file loads A and B ALUOut- cond PCSource = 01 PCWriteCond = 1 An IR-specified register in Register file is written from ALUOut Jump address PCSource = 10 PCWrite = 1 An IR-specified register in Register file is written from MDR Sequenc ing Seq AddrCtl = 11 Choose next μInstr. sequentially Fetch AddrCtl = 00 Go to first μInstr. to begin new instruction Dispatch 1 AddrCtl = 01 Use Dispatch ROM 1 Dispatch 2 AddrCtl = 10 Use Dispatch ROM 2

24. Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 24 Microinstruction Fetch LabelALUSRC1SRC2Reg. Mem.PCWriteSeq. ctrl.ctrl.ctrl. FetchAddPC4 Read PCALUSeq DecodeAddPCExtShftRead Dispatch 1 Microassembler produces the following microcode: 000010 0 0 1 0 1 000 1 011 000110 0 0 0 0 0 000 0 001 ALUOp ALUSrcAALUSrcB RegWrite RegDst MemtoReg MemRead IorD IRWrite MemWrite PCSource PCWrite PCWriteCond Addrctl

25. Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 25 Microprogram for lw and sw LabelALUSRC1SRC2Reg. Mem.PCWriteSeq. ctrl.ctrl.ctrl. LWSW1AddAExtend Dispatch 2 LW2 Read ALUSeq RegWr Write MDRFetch SW2 Write ALUFetch Microprogram consists of four microinstructions.

26. Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 26 Microprogram for R-Type Instruction LabelALUSRC1SRC2Reg.Mem.PCWriteSeq. ctrl.ctrl.ctrl. R1 Funct codeAB Seq RegWrWrite ALUFetch Go to next μInstr. Go to μInstr. Fetch Microprogram consists of two microinstructions.

27. Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 27 Microprogram for beq Instruction LabelALUSRC1SRC2Reg.Mem.PCWriteSeq. ctrl.ctrl.ctrl. BEQ1 SubtAB ALUOut-condFetch If (zero) then PC ← ALUOutGo to μInstr. Fetch Microprogram consists of one microinstruction.

28. Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 28 Microprogram for jump Instruction LabelALUSRC1SRC2Reg.Mem.PCWriteSeq. ctrl.ctrl.ctrl. JUMP1 Jump addressFetch Microprogram consists of one microinstruction.

29. Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 29 μProgram for Multi-Cycle CU LabelALUSRC1SRC2Reg. Mem.PCWriteSeq. ctrl.ctrl.ctrl. FetchAddPC4 Read PCALUSeq Decode1AddPCExtShftRead Disp. 1 LWSW1AddAExtend Disp. 2 LW2 Read ALUSeq RegWr Write MDRFetch SW2 Write ALUFetch R1 FntCd.AB Seq RegWrWrite ALUFetch BEQ1 SubtAB ALUOut-condFetch JUMP1 Jump addressFetch

30. 26-31 to Microcoded Control Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 30 Multicycle Datapath PC Instr. reg. (IR) Mem. Data (MDR) ALUOut Reg. A Reg. B Reg. ALU Register file Memory Addr. Data 4 Sign extend Shift left 2 ALU control 0-5 0-15 16-20 21-25 IorD MemtoReg ALUOp ALUSrcBALUSrcA RegDst IRWrite RegWrite MemWrite MemRead Shift left 2 0-25 28-31 PCSource PCWrite etc. 11-15

31. Microcode Operation μPC is always initialized to 0000 Load starting instruction address in PC Clock control and datapath Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 31

32. Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 32 How Microcode Works Sixteen 18-bit words 4-bit address 0000 16 11 clk 1: Set Datapath for Fetch 4 4 0001 MUX 11 10 01 00 0000 AddrCtl Dispatch ROM 2Dispatch ROM 1 Adder 6 Opcode from IR In clk 2 Address Microcode memory μPC Address select logic Sequencing field lw or sw sw, lw, R, B or J ROM address 0001 in clk 2

33. Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 33 Multicycle Control FSM Instr. decode/reg. fetch/branch addr. ALU operation Write PC on branch condition Write memory data Write jump addr. to PC Write register Read memory data Instr. fetch/ adv. PC Compute memory addr. Write register lw or sw lw sw R B J Start State 0 1 23 45 6 7 8 9 Inputs: 6 opcode bits Outputs: 16 control signals

34. Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 34 Summary Hard-wired control: A finite state machine implemented typically using programmable logic array (PLA) or random logic. Microinstruction: A one-clock instruction that asserts a set of control signals to the datapath and specifies what microinstruction to execute next. Microprogram: A sequence of microinstructions that implements a multicycle (or single cycle) instruction. Microcode: Machine code of a microprogram, generally produced by a microassembler. Microprogrammed or microcoded control: A method of specifying control that uses microcode rather than a finite state machine.

35. Spr 2015, Mar 13... ELEC 5200-001/6200-001 Lecture 8 35 Further on Microprogramming Preceding discussion is based on: D. A. Patterson and J. L. Hennessey, Computer Organization and Design, Second Edition, San Francisco: Morgan-Kaufman, 1998, Chapter 5, pp. 399-410. Terms “microcomputer”, “microarchitecture” and “micropipeline” are not related to microprogramming. Nanoprogramming: Two levels of microprogramming – a “recursive” control: Nanodata Corp., QM-1 Hardware Level Users Manual, 2 nd Ed., Williamsville, NY, 1972. J. P. Hayes, Computer Architecture and Organization, Section 4.4.3, NY: McGraw-Hill, 1978. Virtual machines: Any program can be run on any instruction set using an interpreter. Example, Java.