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Process integration sami.franssila@aalto.fi.

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Presentation on theme: "Process integration sami.franssila@aalto.fi."— Presentation transcript:

1 Process integration

2 Wafer selection active role for the wafer ? passive role ?
thermal conductivity optical transparency flat, smooth mechanical support compatibility with equipment ? thermal limitations ? contamination ? Especially glass in Si fabs !

3 Metal heater processing
Metal sputtering (or evaporation) Photoresist spinning & baking Lithography with resistor mask 4. Resist image development 5. Metal etching 6. Photoresist stripping Can be done on any wafer ! Glass wafers, polymer, ...

4 Diffused heater processing
Thermal oxidation Photoresist spinning & baking Lithography with heater mask Oxide etching Photoresist stripping Wafer cleaning Diffusion (in furnace) New thermal oxidation ! Only applicable on silicon wafers !

5 Diffused vs. metal resistor
Size determined by: -lithography+ -diffusion Always isotropic !! 2 µm linewidth + 1 µm diffusion depth  4 µm wide resistor Size determined by: -lithography+ -etching Can be anisotropic. 2 µm linewidth  2 µm wide resistor

6 Example:solar cell process flow
top metallization anti-reflective coating (ARC) Backside metallization p-substrate p+ diffusion n -diffusion The contact holes in anti-reflective coating are non-critical The metallization alignment to contact holes is critical (in case of misalignment, metal does not fully cover holes, and gases, liquids, dirt can penetrate into silicon)

7 Front end processing wafer selection (p-type) wafer cleaning
thermal oxidation photoresist spinning on front backside oxide etching resist stripping p+ backside diffusion (1019 cm-3) front side oxide etching n-diffusion (1017 cm-3) FRONT END = STEPS BEFORE METALLIZATION backside metallization top metallization antireflection coating (ARC) p-substrate p+ diffusion n -diffusion

8 Backend processing resist spinning on front
metal sputtering on back side resist stripping wafer cleaning PECVD nitride deposition lithography for contact holes etching of nitride metal deposition on front side lithography for front metal metal etching photoresist stripping contact improvement anneal backside metallization top metallization antireflection coating (ARC) p-substrate p+ diffusion n -diffusion BACKEND IS PROCESS AFTER FIRST METAL DEPOSITION

9 Active vs. passive cleaning
Cleanroom (and its subsystems) provide passive cleanliness Wafer cleaning provides active cleaning

10 Wafer cleaning removal of added contamination
ultrapure chemicals (very expensive) particle-free (filtered 0.3 µm) always includes rinsing & drying steps (with ultrapure water and nitrogen)

11 Surface preparation leaves wafer in known surface condition
eliminates previous step peculiarities eliminates waiting time effects Wafer cleaning is the same as surface preparation; it is just a different viewpoint of wafer cleanliness

12 Contact angle θ Ultrahydrophilic (θ ~ 10o) Hydrophilic (θ ~ 70o) Hydrophobic (θ >90o) If surface is hydrophobic, water-based cleaning chemicals will be ineffective.

13 RCA-1 cleaning NH4OH:H2O2:H2O (1:1:5) removes particles
removes organic (polymeric) materials leaves surface hydrophilic

14 RCA-2 cleaning HCl:H2O2:H2O (1:1:6) removes metal contamination
leaves surface hydrophilic

15 Piranha: H2SO4 + H2O2 H2SO4 is a strong oxidant
oxidizing effect is enhanced by addition of peroxide H2O2 Leaves surface with a thin SiO2 layer (= hydrophilic). Nitric acid similar.

16 HF, hydrofluoric acid removes SiO2 leaves surface hydrophobic
Thermal oxidation + HF etching is a really good cleaning method !

17 Equipment: 1- or 2-sided processing
Beam processes 1-sided Immersion processes 2-sided -photon beams (=lithography) -liquids (=wet etching) -atom beams (=evaporation) -liquids (=cleaning) -ion beams (=implantation) -gases (= oxidation, diffusion) -mixture of these (=plasmas) -gases (=CVD)

18 Both side processes Thermal oxidation CVD Wet etching Wet cleaning

19 Single side processes Ion implantation PECVD, RIE

20 Wet etch vs. plasma etch Oxide wet etch in HF
Oxide plasma etch in CHF3 Film removed from backside Backside remains protected

21 Fluidic filters a b c d

22 Fluidic filters (2) Criteria:
Need one or two wafers ? Cost, bonding... Pass size determined by litho ? Bonding ? Flow resistance ? Aperture ratio. Clogging ? Active cleaning ?

23 Alignment and design rules
Example of Overlap rule: Coinciding structures must overlap by (LW/3)

24 Design rules (2) a Overlap rule eliminates alignment errors and mask size errors. b

25 Design rules (3) Minimum linewidth rule Minimum spacing rule
Overlap rules for structures on different layers Electrical rules: Aluminum sheet rsistance 0.03 Ω/sq No rectangular capacitors Breaking design rules ruins your process (=you are expecting too much from the process) Within one layer

26 Self-alignment: CMOS gate

27 Self-alignment: sawtooth grid

28 RCL circuit on silica Au-coil CVD ox-3 CVD ox-2 CVD ox-1 nitride
fused silica CVD ox-3 capacitor Mo resistor SiCr resistor Au-coil nitride

29 Cleaning steps omitted !!
Wafer selection: fused silica to eliminate paracitic capacitance Molybdenum deposition Lithography #1: molybdenum resistor and capacitor bottom plate Molybdenum etching and resist stripping Nitride deposition by LPCVD CVD oxide-1 deposition Sputtering of SiCr high resistivity resistor CVD ox-1 CVD ox-2 fused silica CVD ox-3 capacitor Mo resistor SiCr resistor Au-coil nitride

30 Lithography #2: SiCr resistor pattern
SiCr etching and resist stripping CVD oxide-2 deposition Lithography #3: contact holes to molybdenum Plasma etching of CVD-ox2/CVD-ox-1/nitride and resist stripping Lithography #4: contact holes to SiCr resistor and to capacitor top Wet etching of CVD-ox-2/CVD-ox-1 and resist stripping CVD ox-1 CVD ox-2 fused silica CVD ox-3 capacitor Mo resistor SiCr resistor Au-coil nitride

31 Lithography #5: aluminum pattern Aluminum etching and resist stripping
Aluminum deposition Lithography #5: aluminum pattern Aluminum etching and resist stripping CVD oxide-3 deposition Lithography #6: contact holes to aluminum Etching of CVD-ox-3 and resist stripping Lithography #7: Inductor coil pattern Gold electroplating Resist stripping CVD ox-1 CVD ox-2 fused silica CVD ox-3 capacitor Mo resistor SiCr resistor Au-coil nitride

32 NbN bolometer in SEM Figure courtesy Leif Grönberg, VTT

33 Bolometer Bolometer mask view process flow 6) 2nd lithography
7) Oxide etch 8) Silicon isotropic etch 1) Oxidation 2) Metal deposition 3) Lithography 4) Metal etching 5) Resist strip

34 NbN bolometer in SEM Figure courtesy Leif Grönberg, VTT

35 NbN bolometer with Al pads
Schematic drawing top view Optical microscope image (top view) Schematic drawing (side view)

36 Critical vs. non-critical steps
Bonding defines 1 µm capacitor gap Bonding creates 500 µm channel

37 Order of process steps

38 Order of process steps (2)

39 Protecting wafers from dirt ( cleanrooms & gowning)
from atoms, ions, molecules ( wafer cleaning) from mechanics ( backside & edge protection) from chemicals ( compatibility) from temperature ( thermal budget) from static electricity (ESD shielding)

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