1. HF RM igloo2 development Tullio Grassi, 5 Nov 2014 Univ of Maryland

2. Committed and tested v 01.12 (hex) Added stuff on SVN doc/ folder Tested in bld 904

3. QIE clocks with individual phase control The twelve QIE clocks are sent from the igloo2 to the QIE chips. Inside the igloo2, the clocks are synthesised using a 320 MHz, as if they were normal data lines. Also the data from the QIE10 chips are acquired at 320 MHz (oversampling)  major redesign. At power-up the twelve QIE clocks are often bad, they do not even look like clock signals. Many QIE10 chips will report DLL NoLock = 1. You can fix this simply with a Backplane_RST (or also changing the set value of each phase). I tried many fw to have them good at powerup, but no success.

4. First test of phase control of the QIE (sampling) clocks Probed with the oscilloscope: MClk from the backplane as trigger; QIE1 and QIE2 clocks on test points (they look identical). settingclk1_ph [ns]step [ns] 00 11.57 23.1 1.53 34.8 1.7 46.26 1.46 57.98 1.72 69.4 1.42 711.03 1.63 812.48 1.45 914.23 1.75 1015.74 1.51 1117.28 1.54 1218.74 1.46 1320.37 1.63 1422 1.63 1523.64 1.64

5. Data acquired with uHTRtool RAW0 RAW1 100BC 00500 00604 0FF05 0FFFF 00000 100BC 00555 00403 0FF04 0FFFF 00000 100BC 005AA 00604 0FF04 0FFFF 00000 100BC 005FF 00403 0FF04 0FFFF 00000 100BC 00500 00604 0FF05 0FFFF 00000 100BC 00555 00403 0FF04 0FFFF 00000 CapIds are good The rest looks good as well 4-channel data format

6. Mysteries and problems about igloo2 on the latest version, many Differential Input I/O Pairs changed from registered to non- registered [see file HF_RM_igloo2_top_bankrpt.rpt ]. Why ? according to the Max delay analysis performed by the sw tool, our 320 MHz clock does not meet the frequency constraint: in v 1.12 the simulated frequency is 278 MHz in worst-case conditions, and 318 MHz in typical case (the part number has Speed Grade -1, which is the fastest one) DEVRST_N input can be important but is not clear (seems more like a power_enable than a reset) Timing constrains are still confusing. Related to this, Synopsys has changed format for the timing constraints (sdf format is now obsolete). Microsemi Libero will probably follow. And many others…

7. There are still a mysteries also on the Bridge FPGA Issuing a DEVRST_N (Bottom_RESET_N) from the Bridge FPGA to the igloo2 often upsets the Bridge FPGA  recover with a power-cycle. All these problems are probably more critical for HE than HF.