1. Chapter 4 The Von Neumann Model

2. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model2 Concepts to Learn… Computer Architecture Von Neumann vs. Harvard MSP430 Architecture RISC / CISC Anatomy of an Instruction MSP430 Instructions Instruction Cycles Clocks MSP430 Finite State Machine

3. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model3 Forecasting Computer Technology “I think there is a world market for maybe five computers.” Thomas Watson, IBM Chairman, 1943 “Computers in the future may weigh no more than 1.5 tons.” Popular Mechanics, 1949 “There is no reason anyone would want a computer in their home.” Ken Olsen, DEC founder, 1977 “DOS addresses only 1 MB of RAM because we cannot imagine any applications needing more.” Microsoft, 1980 “The 32-bit machine would be an overkill for a personal computer.” Sol Libes, ByteLines, 1981 “640K ought to be enough for anybody.” Bill Gates, 1981

4. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model4 The Von Neumann Computer Control Unit Program CounterInstruction Register INPUT * keyboard * mouse * scanner * A/D * serial * disk OUTPUT * monitor * printer * LEDs * D/A * disk Memory Processing Unit ALU Registers Control Datapath Von Neumann proposed this model in 1946 The Von Neumann model: Program instructions and Data are both stored as sequences of bits in computer memory Address BusData Bus Von Neumann

5. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model5 Memory Interface Memory Address Bus Memory Address Register (MAR) stores the memory address for the address bus (address space) used to address peripherals as well as memory Memory Data Bus Memory Select (MSEL) connects memory to the data bus (addressability) Memory Write Enable (MWE) is the control signal that is asserted when writing to memory bi-directional bus Von Neumann

6. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model6 Memory Terminology Address Space = amount of data that can be stored (also called the memory size) Addressability = number of bits stored in each memory location 1 byte= 8 bits 1 Kilobyte (KB)= 2 10 bytes = 1024 bytes 1 Megabyte (MB)= 2 20 bytes 1 Gigabyte (GB)= 2 30 bytes 1 Terabyte (TB)= 2 40 bytes 1 Petabyte (PB)= 2 50 bytes 1 Exabyte (EB)= 2 60 bytes Von Neumann

7. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model7 MSP430 Architecture

8. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model8 The Processing Unit Performs the arithmetic and logical operations ALU = Arithmetic and Logic Unit Arithmetic operations: add, subtract, compare Logical operations: and, xor, bit Sets condition codes The word length of a computer is the number of bits processed by the ALU. Includes a small amount of very fast memory close to the ALU (operand registers, register file). MSP430 Architecture

9. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model9 The Control Unit The control unit directs the execution of the program The program counter or PC points to the next instruction to be executed The instruction register or IR contains the currently executing instruction The status register or SR contains information about the last instruction executed as well as system parameters The control unit prevents bus conflicts and timing/propagation problems The control unit is a Finite State Machine driven by a clock MSP430 Architecture

10. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model10 Interrupt vectors Upper 16 words of Flash Flash / ROM Used for both code and data RAM Volatile storage Peripherals 0100h – 01FFh 16-bit peripherals 0010h – 00FFh 8-bit peripherals Special Function Registers Lower 16 bytes MSP430 Memory MSP430 Architecture

11. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model11 Input and Output Used to get information in and out of the computer. External devices attached to a computer are called peripherals. MSP430 Architecture

12. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model12 The MSP430 Processing Unit Memory Unit Control Unit I/O Unit MSP430 Architecture

13. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model13 RISC / CISC Instruction Set Emphasis on software Single-clock Reduced instructions Low cycles/second Large code sizes More transistors on memory registers Pipelining friendly Emphasis on hardware Multi-clock Complex instructions Small code sizes High cycles/second More transistors for complex instructions Compiler friendly CISC RISC RISC / CISC

14. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model14 MSP430 RISC/CISC Instruction Set RISC / CISC

15. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model15 Anatomy of an Instruction Opcode What the instruction does - Operator Source Operand 1st data object manipulated by the instruction Destination Operand 2nd data object manipulated by the instruction Where results of operation is stored. Addressing Modes Computer Instructions

16. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model16 3 Instruction Formats MSP430 Instructions

17. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model17 Double Operand Instructions MSP430 Instructions

18. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model18 Single Operand Instruction MSP430 Instructions

19. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model19 Jump Instructions MSP430 Instructions

20. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model20 Addressing Modes MSP430 Instructions

21. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model21 The Instruction Cycle INSTRUCTION FETCH Obtain the next instruction from memory DECODE Examine the instruction, and determine how to execute it SOURCE OPERAND FETCH Load source operand DESTINATION OPERAND FETCH Load destination operand EXECUTE Carry out the execution of the instruction STORE RESULT Store the result in the designated destination Not all instructions require all six phases Instruction Cycles

22. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model22 The Instruction Fetch Phase Computer programs consist of sequence of instructions each instruction = 1-3 Binary Words stored in memory as 1’s and 0’s called machine code. Instructions are fetched from memory using the program counter (PC) as the address of the memory location. Program counter “increments” for each instruction. Instruction Cycles

23. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model23 Instruction Decode Phase Pick apart the instruction stored in the IR control unit in control logic does all this Determines instruction format operation operand sources operand destination Combinational logic (ie. Does not require a clock cycle.) Instruction Cycles

24. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model24 Source Operand Fetch Phase Instruction format defines addressing mode Register mode - Rn Indexed mode - x(Rn) Symbolic mode - addr Absolute mode - &addr Indirect register mode - @Rn Indirect autoincrement mode - @Rn+ Immediate mode - #n Constant Generator Instruction Cycles

25. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model25 Destination Operand Fetch Phase Instruction format defines addressing mode Register mode - Rn Indexed mode - x(Rn) Symbolic mode - addr Absolute mode - &addr Instruction Cycles

26. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model26 Execute Phase ALU is combinational logic and does not require a clock Some instructions are multi-functional and require several operations PUSH - stack decremented RETI - status register restored from stack, stack incremented, program counter restored from stack, stack incremented CALL - stack decremented, program register saved on stack. Instruction Cycles

27. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model27 Store Phase ALU results are stored in register or memory Location of destination operand is the target of the result of the instruction. Instruction Cycles

28. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model28 Clocks With a clock cycle, the processor performs an action that corresponds to an instruction phase. CPI (Cycles Per Instruction) is the average number of clock cycles required for a microprocessor to execute an instruction. A microprocessor power is characterized by the number of instructions per second that it is capable of processing. MIPS (millions of instructions per second) is the unit used and corresponds to the processor frequency divided by the cycles per second (CPI). Clocks

29. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model29 Faster steps do not necessarily mean shorter travel time. Faster Clock  Shorter Running Time Clocks

30. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model30 Basic Clock System Basic Clock Module provides the clocks for the MSP430 devices Clocks

31. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model31 Multiple Clocks Clocks

32. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model32 Stopping the Clock Control unit will repeat instruction processing sequence as long as clock is running If not processing instructions from your application, then it is processing instructions from the Operating System (OS) To stop the computer, set the CPUOFF bit in the status register (R2) - disables MCLK Clocks

33. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model33 MSP430 Finite State Machine MPS430 FSM

34. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model34 Finite State Machine MPS430 FSM

35. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model35 Finite State Machine MPS430 FSM

36. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model36 Von Neumann In Review Programs are stored in memory as instructions instructions are simply collections of 1’s and 0’s our MSP430 machine has 16-bit instructions Data is also stored in memory as 1’s and 0’s A program is executed by fetching next instruction from memory decoding it fetching its operands doing the requested operation and storing the result Review

37. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model37 The Von Neumann Bottleneck You may hear of the term “Von Neumann Bottleneck” All instructions / data has to be fetched from memory the path to memory is a bottleneck In spite of this, the Von Neumann model is today’s computing model Review

38. BYU CS/ECEn 124Chapter 4 - The Von Neumann Model38