1. Running a Quantum Circuit at the Speed of Data Nemanja Isailovic, Mark Whitney, Yatish Patel, John Kubiatowicz U.C. Berkeley QEC 2007

2. The Impact of QEC H X QEC Step Zero Ancilla Prep time Serial Latency Parallel Latency Data Involvement in QEC Step

3. The Speed of Data Non-Transversal Logical Gate –Zhou et al., Phys. Rev. A, 62(5):52316 Ideally, execution time determined solely by data Non-Transversal Ancilla Prepare Data Involvement time hardware

4. Limited BW Graph 32-bit Quantum Carry-Lookahead Adder in Ion Traps –Varying rate at which encoded zero ancillae are provided for QEC –Conclusion: design architecture with “ancilla factories”

5. Idealized Qalypso Architecture Dense data region –Data qubits only –Local communication Shared Ancilla Factories –Distributed to data as needed –Fully multiplexed to all data –Output ports ( ): close to data –Input ports ( ): may be far from data, since recycled qubits have irrelevant state Goals –Design ancilla factories –Answer Question: How much hardware is needed for ancilla generation to run at the speed of data?

6. Our Quantum CAD Toolset Automated toolset to assist in architecture design –Ion trap technology –Local gates: two qubits in the same trap –Basic block abstraction: to avoid unknown electrode details Our basic layout blocks straight3-way4-wayturn gate locations Dr. Hensinger, University of Sussex 3-way intersection

7. Level 1 [[7,1,3]] QEC Circuits Identical Circuits Steane, Multiple-Particle Interference and QEC

8. Zero Ancilla Factory Design I “In-place” ancilla preparation Encoded AncillaVerification Qubits Ancilla factory consists of many of these –Encoded ancilla prepared in many places –But we want input and output ports In-place Prep In-place Prep In-place Prep In-place Prep

9. Zero Ancilla Factory Design II Pipelined ancilla preparation: break into stages –Match physical qubit bandwidth between stages for high utilization –Steady stream of encoded ancillae at output port Physical 0 Prep CNOTs Cat Prep Crossbar CNOTs Cat Prep Crossbar Verif Physical 0 Prep X/Z Correct Crossbar X/Z Correct Junk Physical Qubits Good Encoded Ancillae Recycle cat state qubits and failures Recycle used correction qubits

10. Area Needs for Ancilla Preparation

11. Practical Qalypso Architecture Multiple Data Regions –Each serviced by local ancilla factories –Communication network moves data between regions (not shown) –Data regions as large as possible to get benefits of minimizing inter-region movement and multiplexing ancilla factory output

12. Summary Investigated removing ancilla generation from critical path –Operations on data qubits dictate performance –Tradeoff in ancilla bandwidth vs execution speed Architectural approach: ancilla factories –Match production bandwidth to needs of data –Pipelining places output ports close to data Qalypso architecture –Dense data regions with local communication –Ancilla factories segregated from data Multiplexing between factories and data Input and output ports –Layout investigation => ancilla generation dominates area