Transport and inertial delay Assignment statements

Transport and inertial delay Assignment statements
bus waveforms Transport and inertial delay Assignment statements more on Variables and signals delta and simulation How VHDL simulator works

This lecture is very important
You can learn syntactical aspects from manual but here we discuss the principle of how the simulator works. Therefore we will show many examples and will discuss some aspects several times from different points of view. Please make sure that you really understand all concepts here.

Event Driven Simulation and the first encounter with delta

Simulation Loop is based on executing signals from time queue

Process Triggering

Some Rules for Processes
These rules have to be remembered. Our next slides will explain better why it is so…

An Infinite Loop Remember: processes repeat indefinitely with new data coming. But here is not new data

A Common Error of users It is safe to add all input signals from your circuit to the sensitivity list. You may only slow down the simulator.

Delta Time

Two-Dimensional Time

A Delta-Time Infinite Loop
This is wrong way to make a clock.

Behavioral Modeling in VHDL
VHDL behavior Sequential Statements Concurrent Statements These are two fundamental behaviors from which all simulation and synthesis models work

VHDL behavior models: concurrent sequential

Sequential v.s. Concurrent Statements
VHDL is inherently a concurrent language All VHDL processes execute concurrently Concurrent signal assignment statements are actually one-line processes Processes are re-executed if any signal in its sensitivity list is changed VHDL statements execute sequentially within a process Concurrent processes with sequential execution within a process offers maximum flexibility Supports various levels of abstraction Supports modeling of concurrent and sequential events as observed in real systems

VHDL behavior: Concurrent, sequential and processes

Concurrent Statements

Concurrent Statements
Basic granularity of concurrency is the process Processes are executed concurrently Concurrent signal assignment statements are one-line processes Mechanism for achieving concurrency : Processes communicate with each other via signals Signal assignments require delay before new value is assumed Simulation time advances when all active processes complete Effect is concurrent processing i.e. order in which processes are actually executed by simulator does not affect behavior Other than in last slide Concurrent VHDL statements include : Block, process, assert, component instantiation

Processes

Behavioral sequential statements

What specifically are the sequential statements?

Initialization of processes

Execution of parallel processes
The processes here have no sensitivity list but have wait statements

Model of Processes: waiting for events to occur

Signals and variables in Processes

Communication Between Processes via Signals
Explain this slide well showing what happens when I have many statements after DONE_FIRST Discuss also how senthisizatoin list is changed to WAIT UNil These are executed when first process allows

All these assignments executed in no time
Many assignment Statements D  1 statements Wait until D=‘1’ Wait 10nS Diagrams like this are useful to visualize time in processes and how they interact Process FIRST Process NEXT

Another example D  1 V  0 2 A <= 8 V=1 Wait until D=‘1’ 10
Wait 10nS From next iteration of process NEXT D  0 V  0 Wait 10nS From first iteration of process NEXT Process NEXT Process FIRST Wait 2nS 2 10 D=1 A=8 V=1 -> 0 D=1 A=8 V=0 D=0 A=8 V=1 From next iteration of process NEXT

V=0 D=1 2nS A=8,V=1 10nS 10nS D=0

Signals Communicate in Between the Processes: signals propagate when processes are waiting
Change wording? Signals propagate within processes and between processes!

Signals Assigned After Processes Run: waiting processes can awake another processes

Example of role of WAIT in a process
Assignment of value to signal C will be discussed in next slides No delay of elements Observe that there is no sensitivity list here. When A or B change, new value of variable TEMP is immediately calculated. It is used to calculate output signal C, not shown. This is just a trivial example. More will come.

Process with Signals

Sensitivity List It is important to understand that change of c will not initiate the process here!

Process with Sensitivity List
We declare arbitrary delays You can use variables to simplify description or define exact timing

Compilation and Simulation of VHDL Code
Compiler (Analyzer) – checks the VHDL source code does it conforms with VHDL syntax and semantic rules are references to libraries correct Intermediate form used by a simulator or by a synthesizer Elaboration create ports, allocate memory storage, create interconnections, ... establish mechanism for executing of VHDL processes compilation Internal data structures synthesis

VHDL Modeling Concepts
Semantics (meaning) of VHDL is heavily based on SIMULATION A design is described as a set of interconnected modules A module could be another design (component) or could be described as a sequential program (process)

VHDL Program Structure: visualization of concurrency
These modules are simulated concurrently through signals This means that they are all simulated in the same time before next delta comes

A general VHDL design with modules: another visualization of concurrency
Entity … is … End entity; I1 O1 I2 IO1 s1 component concurrent assignment I1 O1 s2 architecture … of … is ... begin … end; s3 s4 s8 s9 s6 process 1 process 2 concurrent assignment I2 IO1 s5 s7 This diagram helps to visualize how process communication works - concurrency

VHDL Simulator start Init t = 0 more event stop get earliest event delta delay advance time update signals This diagram helps to visualize how process communication works - concurrency execute triggered processes during process execution, new events may be added

Process Statements FORMAT PROCESS_LABEL: process
-- declarative part declares functions, procedures, types, constants, variables, etc begin -- Statement part sequential statement; wait statement; -- eg. Wait for 1 ms; or wait on ALARM_A; … wait statement; end process; Flow of control This diagram helps to visualize how process communication works - concurrency

Modeling Timing in VHDL
VHDL can be used to specify different aspects of timing characteristics of hardware devices: propagation delay of signals operational time Why we need timing? The type “time” is a pre-defined physical type. Mainly useful for modeling device timing characteristics Can also be used to specify timing requirements, e.g., setup and hold times of devices. You can parameterize timing properties of an entity.

EXAMPLE: Process Declaration of Clock Generator
Clock_gen: process (clk) is begin if clk = ‘0’ then clk <= ‘1’ after T_pw, ‘0’ after 2*T_pw; endif; end process clock_gen; 2*T_pw T_pw

Waveform and Driver Simulator uses drivers for signals
A driver of a signal contains a current value and a waveform representing projected future values. Waveform elements are appended to a driver whenever a signal assignment is executed. How to describe a waveform? Use “after”

Using Nested IFs and ELSEIFs
Simulator has also to understand semantics of statements like IF Advise is to draw yourself flowchart like this to understand better

What Happens in Simulation?
After examples discussed, we now understand better what are events and how they are scheduled. Details of implementation are not important at this time.

Timing Model in VHDL

Timing Model in VHDL VHDL uses a simulation cycle to model the stimulus and response nature of digital hardware We will introduce 3 models for delay Start Simulation Delay Update Signals Execute Processes The VHDL timing model controls the stimulus and response sequence of signals in a VHDL model. At the start of a simulation, signals with default values are assigned those values. In the first execution of the simulation cycle, all processes are executed until they reach their first wait statement. These process executions will include signal assignment statements that assign new signal values after prescribed delays. After all the processes are suspended at their respective wait statements, the simulator will advance simulation time just enough so that the first pending signal assignments can be made (e.g. 1 ns, 3 ns, 1 delta cycle). After the relevant signals assume their new values, all processes examine their wait conditions to determine if they can proceed. Processes that can proceed will then execute concurrently again until they all reach their respective wait conditions. This cycle continues until the simulation termination conditions are met or until all processes are suspended indefinitely because no new signal assignments are scheduled to unsuspend any waiting processes. End Simulation 32

Types of Delay in VHDL All VHDL signal assignment statements prescribe an amount of time that must transpire before the signal assumes its new value This prescribed delay can be in one of three forms: Transport -- prescribes propagation delay only Inertial -- prescribes minimum input pulse width and propagation delay Delta -- the default if no delay time is explicitly specified There are several types of delay in VHDL, and understanding how delay works in a process is key to writing and understanding VHDL. It bears repeating that any signal assignment in VHDL is actually a scheduling for a future value to be placed on that signal. When a signal assignment statement is executed, the signal maintains its original value until the time for the scheduled update to the new value. Any signal assignment statement will incur a delay of one of the three types listed in this slide. Input Output delay 33

Concepts of Delays and Timing
The time dimension in the signal assignment refers to simulation time in a discrete event simulation There is a simulation time clock When a signal assignment is executed, the delay specified is added to current simulation time to determine when new value is applied to signal Schedules a transaction for the signal at that time output input

More on inertial and transport models
Inertial delay Model the time lag between stable inputs and valid output of a device Representative of combinational logic elements Pulses smaller than transmission delay are suppressed Default model for VHDL descriptions Transport delay Model a pure delay mechanism All pulses are transmitted Used for transmission lines or elements with clock- cycle latency

Inertial versus transport delay
How small should be the glitch to be distinguished by inertial and transport? We will answer in next slides Observe the spike is lost in A when we use AFTER Observe the spike is NOT lost in B when we use TRANSPORT

Transport Delay Delay must be explicitly specified by user
Under this model, ALL input signal changes are reflected at the output Delay must be explicitly specified by user Keyword “TRANSPORT” must be used Signal will assume its new value after specified delay -- TRANSPORT must be specified Output <= TRANSPORT NOT Input AFTER 10 ns; Input Output The keyword TRANSPORT must be used to specify a transport delay. Transport delay is the simplest in that when it is specified, any change in an input signal value may result in a new value being assigned to the output signal after the specified propagation delay. Note that no restrictions are specified on input pulse widths. In this example, Output will be an inverted copy of Input delayed by the 10ns propagation delay regardless of the pulse widths seen on Input . Input Output As we see, spikes are not lost 34

Specifying Delays: Inertial Model
Inertial Delay Model reflects physical inertia of physical systems glitches of very small duration not reflected in outputs SIG_OUT <= not SIG_IN after 7 nsec --implicit SIG_OUT <= inertial ( not SIG_IN after 7 nsec ) Logic gates exhibit lowpass filtering 3 ns 10ns SIG_IN 2ns SIG_OUT 9 ns 19 ns

Inertial Delay Provides for specification of input pulse width, i.e. ‘inertia’ of output, and propagation delay : Inertial delay is default and REJECT is optional : target <= [REJECT time_expression] INERTIAL waveform; Output <= NOT Input AFTER 10 ns; -- Propagation delay and minimum pulse width are 10ns The keyword INERTIAL may be used in the signal assignment statement to specify an inertial delay, or it may be left out because inertial delay is used by default in VHDL signal assignment statements which contain “after” clauses. If the optional REJECT construct is not used, the specified delay is then used as both the ‘inertia’ (i.e. minimum input pulse width requirement) and the propagation delay for the signal. Note that in the example above, pulses on Input narrower than 10ns are not observed on Output. Here reject is not used Input Output Input Output Here we do not write INERTIAL because it is a default. Signal shorter than 10ns is avoided 35

Inertial Delay with REJECT
Note that REJECT feature is new to VHDL Example of gate with ‘inertia’ smaller than propagation delay e.g. Inverter with propagation delay of 10ns which suppresses pulses shorter than 5ns Output <= REJECT 5ns INERTIAL NOT Input AFTER 10ns; Example of gate with ‘inertia’ smaller than propagation delay e.g. Inverter with propagation delay of 10ns which suppresses pulses shorter than 5ns Input The REJECT construct is a new feature to VHDL introduced in the VHDL standard. The REJECT construct can only be used with the keyword INERTIAL to include a time parameter that specifies the input pulse width constraint. Prior to this, a description for such a gate would have needed the use of an intermediate signal with the appropriate inertial delay followed by an assignment of this intermediate signal’s value to the actual output via a transport delay. Output Because here we clearly specify REJECT 5ns, only signals 5ns or shorter are rejected and 7ns is not rejected 36

A problem with inertial delay
Output has propagation delay of 4ns buffer

How the simulator works.
Delta

Delta Delay Delta Delay is the default signal assignment propagation delay in case that no delay is explicitly prescribed VHDL signals assignment cannot take place immediately Delta is an infinitesimal VHDL time unit so that all signal assignments can result in signals assuming their values at some future time E.g. Delta delay supports a model of concurrent VHDL process execution Order in which processes are executed by simulator does not affect simulation output Output <= NOT Input; -- Output assumes new value in one delta cycle VHDL allows the designer to describe systems at various levels of abstraction. As such, timing and delay information may not always be included in a VHDL description. A delta (or delta cycle) is essentially an infinitesimal, but quantized, unit of time. The delta delay mechanism is used to provide a minimum delay in a signal assignment statement so that the simulation cycle described earlier can operate correctly when signal assignment statements do not include explicitly specified delays. That is: 1) all active processes can execute in the same simulation cycle 2) each active process will suspend at wait statement 3) when all processes are suspended simulation is advanced the minimum time necessary so that some signals can take on their new values 4) processes then determine if the new signal values satisfy the conditions to proceed from the wait statement at which they are suspended 37

Delta Delay An Example without Delta Delay
What is the behavior of C? A IN: 1->0 C We do not like such idea of simulator B 1 AND gate evaluated first: IN: 1->0 A: 0->1 C: 0->1 B: 1->0 C: 1->0 For this discussion, assume that the above circuit does not specify any delays, and that there is no delta delay mechanism. In such a case, the order in which model processes (or components) are executed will affect the model outputs. Consider the example above in which there is a 1 to 0 transition at the input of the AND while the other input to the NAND gate is a constant 1. What is the behavior of C? Note that in the case on the left where the NAND gate is evaluated before the AND gate, C can remain at its quiescent value of 0. However, in the case on the right we see that if the AND gate is evaluated before the NAND gate, a glitch is seen at C (i.e. a static-0 hazard is observed). It is generated because the NAND gate has not yet been updated to its new value which will subsequently cause C to become 0. Therefore, C initially goes to 1 and will only go to 0 after the NAND gate drives its output to 0. Therefore, if the order of execution is arbitrary, the behavior of the system may be unpredictable. [Perry94], pp NAND gate evaluated first: IN: 1->0 A: 0->1 B: 1->0 C: 0->0 Glitch generated 38

Delta Delay An Example with Delta Delay
What is the behavior of C? A IN: 1->0 C B 1 Using delta delay scheduling Time Delta Event 0 ns IN: 1->0 eval INVERTER A: 0->1 eval NAND, AND B: 1->0 C: 0->1 eval AND C: 1->0 1 ns Gates that are successors of gate that changed signal value are evaluated In this example, each signal assignment requires one delta cycle delay before the signal assumes its new value. Also note that more than one process can be executed in the same simulation cycle (e.g. both the NAND process and the AND process are executed during delta 2). Following the sequence of events defined by the VHDL simulation cycle, the 1-0 transition on IN allows the INVERTER process to be executed which results in a 0-1 transition being scheduled on A one delta cycle in the future. The INVERTER process then suspends. Since all process are suspended, simulation time advances by one delta cycle so that A can assume its new value. The new value of A allows the NAND and AND processes to be executed. Because the value of A will not change again during simulation time delta 2, it doesn’t matter whether NAND or AND is evaluated first. In either case, the NAND process leads to a 1 being scheduled for C and a 0 being scheduled for B, both one delta cycle in the future. After the assignments are scheduled, NAND and AND suspend again. Again, simulation time advances by one delta cycle so that B and C can assume their new values. The new value of B causes the AND process to be evaluated again. This time, a 0 value is scheduled to be assigned to C one delta cycle in the future, and the AND process can then suspend. Finally, simulation time advances by one delta cycle so that C can assume its new, and final value. Based on [Perry94], pp 22-24 39

Time modelling- delta delay . 1. What is wrong with old simulators?
Clock changes from 0 to 1 As we see in this example the result of simulation depends on order of evaluating gates. This is bad. AND first evaluation NAND first evaluation With this order of evaluation a glitch in signal D is created which means clocking One more clock is generated - this is bad. As we see, timing behavior simulated depends on the gate evaluation order This is good again

Time modelling- delta delay . Delta delay of VHDL solves the problem.
This is levelized evaluation from inputs to outputs Many delta units of time passed but only one unit of time reported to the user delta Delta is as close to zero as we want

Delta Delay: instability time
This example shows use of delta to simulate latch. Here delay is declared using after If no delay time is specified, a delta delay is assumed for any signal assignment. Delta delay represents an infinitesimal delay, less than any measurable time (i.e., femtoseconds), but still larger than zero. An example 5ns Black are instability times These are moments of time

Signals vs Variables: signal used for Out_1
A key difference between variables and signals is the assignment delay ARCHITECTURE sig_ex OF test IS SIGNAL a, b, c, out_1, out_2 : BIT; BEGIN PROCESS (a, b, c, out_1) out_1 <= a NAND b; out_2 <= out_1 XOR c; END PROCESS; END sig_ex; signal a b Out_1 c Out_2 Time a b c out_1 out_2 1+d 1+2d time a b c To review, note that some delay must transpire after a VHDL signal assignment statement before the signal assumes its new value. Examples will be used in this and the next slide to illustrate the difference between signals and variables. The example shown above utilizes signals. The table indicates the values for the various signals at the key times in the example. At time 1, a new value of 1 is observed on a. This causes the process sensitivity list to fire and results in a 0 being assigned to out_1. The signal assignment statement for out_2 will also be executed but will not result in a new assignment to out_2 because neither out_1 nor c will be changed at this time. At time 1+d (i.e. 1 plus 1 delta cycle), out_1 assumes its new value causing the process sensitivity list to fire again. In this process execution, the statement for out_1 will be executed again but no new assignment will be made because its right hand side parameters have not changed. The out_2 assignment statement, however, results in a 1 being assigned to out_2. At time 1+2d, out_2 assumes its new value of 1. This example, then, requires 2 delta cycles and two process executions to arrive at its quiescent state following a change to a (or b, for that matter). out_1 out_2 Symbol d represents delta 1 1+d 1+2d [MG90] 57

Signals vs Variables (Cont.): Variable used for out_3
ARCHITECTURE var_ex OF test IS SIGNAL a,b,c,out_4 : BIT; BEGIN PROCESS (a, b, c) VARIABLE out_3 : BIT; out_3 := a NAND b; out_4 <= out_3 XOR c; END PROCESS; END var_ex; variable a b Out_3 c Out_4 Out_3 is a variable so the change is immediate as shown by red arrow Time a b c out_3 out_4 1+d In this example, variables are used to achieve the same functionality as the example in the previous slide. In this example, however, when there is a change in a at time 1, out_3 will assume its new value at time 1 because it is a variable, and VHDL variable assignment statements result in the new values being assumed immediately. The new value for out_4, therefore, will be calculated with the new out_3 value and results in an assignment to a value of ‘1’ being scheduled for one delta cycle in the future. Also note, however, that in this example, the order in which the statements appear within the process is important because the two statements are executed sequentially, and the process will only be executed once as a result of the single change in a. a b c This example has no any other meaning, it just has to explain the timing of variables and signals in a simulator a,b,c,out_4 are signals but out_3 is a variable out_3 out_4 1 1+d 58

Delta Delay and the simulator in more detail
If no future time is specified, VHDL automatically assumes a small time delay. This delay is the delta delay. The smallest unit of time i.e. 0 fs. Delta causes changes to occur only in the future Delta is consistent with the definition of signals. Mechanism Assignment schedules a transaction The transaction is applied after the process suspends. Process does not see the effect until it resumes next time.

How it works? Recollect simulator kernel. Two phases :
Signal update phase Process execution phase. Signal update phase updates the values of the signals at the current simulation time. This may trigger events. Process execution phase responds to the events and they execute.

Why Delta Delay? Assignments are done in the process execution phase. Eg. X <= 10; Transaction is not applied immediately. It can be done only in the signal update phase. When all processes are suspended, simulation time is updated. Only now is the transaction applied.

Simulation Cycle Revisited Sequential vs Concurrent Statements
VHDL is inherently a concurrent language All VHDL processes execute concurrently Concurrent signal assignment statements are actually one-line processes VHDL statements execute sequentially within a process Concurrent processes with sequential execution within a process offers maximum flexibility Supports various levels of abstraction Supports modeling of concurrent and sequential events as observed in real systems In essence, VHDL is a concurrent language in that all processes execute concurrently. All VHDL execution can be seen as taking place inside processes; concurrent signal assignment statements have already been described as being equivalent to one-line processes. Within a process, however, VHDL adheres to a sequential mode of execution where statements within a process are executed in "top-to-bottom” fashion until the process suspends at a wait statement. This simultaneous support of concurrent and sequential modes allows great flexibility in modeling systems at multiple levels of design and description abstraction. 60

This example will illustrate simulating a 4-bit Adder

Here is the structural description of 4-bit Adder

4-bit Adder – Simulation and analysis of deltas

Next example will show Modeling Flip-Flops Using VHDL Processes
Whenever one of the signals in the sensitivity list changes, the sequential statements are executed in sequence one time General form of process

JK Flip-Flop Model Animation and details in next slide

Notes to the JK Flip-Flop Model

Another simulation example to Recall on Delta Delay
Default signal assignment propagation delay if no delay is explicitly prescribed VHDL signal assignments do not take place immediately Delta is an infinitesimal VHDL time unit so that all signal assignments can result in signals assuming their values at a future time E.g. Supports a model of concurrent VHDL process execution Order in which processes are executed by simulator does not affect simulation output Output <= NOT Input; -- Output assumes new value in one delta cycle VHDL allows the designer to describe systems at various levels of abstraction. As such, timing and delay information may not always be included in a VHDL description. A delta (or delta cycle) is essentially an infinitesimal, but quantized, unit of time. The delta delay mechanism is used to provide a minimum delay in a signal assignment statement so that the simulation cycle described earlier can operate correctly when signal assignment statements do not include explicitly specified delays. That is: 1) all active processes can execute in the same simulation cycle 2) each active process will suspend at wait statement 3) when all processes are suspended simulation is advanced the minimum time necessary so that some signals can take on their new values 4) processes then determine if the new signal values satisfy the conditions to proceed from the wait statement at which they are suspended

Simulation Example illustrating delta
Queue for A Queue for B

Illustration of force and timing diagram in Simulation of the VHDL Model
All forced signals here Simulation command file: Force clk Force X Waveforms:

Structural Model of State Machine
Package bit_pack is a part of library BITLIB – includes gates, flip-flops, counters

Simulation of the Structural Model
Simulation command file: Waveforms:

One More Simulation Example: gate timing
Continued

VHDL simulation of gates with delays
From force

The same circuit but another description for simulation
Now simulator reacts to changes of si signals Order does not matter because we are in architecture and we are executing concurrent statements and not inside a process!

Now we see internal delays

Third description of this example
Change of si creates no event for this process

Differences between CSA and Process
Change of out1, out2 repeats simulation Change of out1, out2 does not repeat simulation

Signals and Variables X is signal X is variable
X is variable so changes immediately and next equation takes new value and not old value as in the code from the left

Variables Variables Inside Processes
Can be altered using variable assignment statements Updating takes place immediately Can be declared only within Processes and Functions Variables Inside Processes Variables inside processes are static Assigned value is stored till next call. Variables inside functions and procedures are not static

Signals Represent data values on physical lines in circuits.
Models the response in actual circuits accurately Does not change values immediately. Assignment does not affect the value immediately. Always occurs sometime in the future – can be at the same simulation time though. Future time at which signal is affected can be explicitly stated. Waveform can also be specified.

Variable assignment statement
Signal assignment wait

Sequential Statements
Variable assignment statement Signal assignment If statement Case statement Loop statement Next statement Exit statement Null statement Procedure call statement Return statement Assertion statement

Variable_assignment_statement ::= target:=expression; architecture RTL of VASSIGN is signal A, B, J : bit_vector(1 downto 0); signal E, F, G : bit; begin p0 : process (A, B, E, F, G, J) variable C, D, H, Y : bit_vector(1 downto 0); variable W, Q : bit_vector(3 downto 0); variable Z : bit_vector(0 to 7); variable X : bit; variable DATA : bit_vector(31 downto 0); begin ... end process end RTL; We declare various types of variables inside the process

signal A, B, J : bit_vector(1 downto 0); signal E, F, G : bit; p0 : process (A, B, E, F, G, J) -- A, B, J, D, H : bit_vector E, F, G : bit begin C := "01"; X := E nand F; Y := H or J; Z(0 to 3) := C & D; Z(4 to 7) := (not A) & (A nor B); D := ('1', '0'); W := (2 downto 1 => G, 3 => '1', others => '0'); DATA := (others => '0'); end process; Variable assigned to a signal The same signal G (a bit) goes to two bits concatenation Make note of mapping notation.. Bit G assigned to two bits. Here we assign signals to variables

Formal Syntax of a signal assignment statement
VHDL syntax description in metalanguage Signal_assignment_statement ::= target<=[transport]waveform_element{,waveform_element}; waveform_element::= value_expression[after time_expression]|null[after time_expression]

WAIT STATEMENT AND TIMING
Perhaps the most difficult to understand statement of VHDL. If you do not understand it , you will have troubles to interpret timing results from simulation and you will be not able to do good behavioral descriptions

Common student mistake, may be because of syntax mistake
WAIT statement Three types of WAIT Common student mistake, may be because of syntax mistake

Example of WAIT statement

The wait statement

Equivalent Processes

“Wait Until” and “Wait for”

Signal Declarations Signals must not be declared inside a process or subprogram. Ports must always be signals. Models sub-system communication correctly.

Example: Variables vs signals
Signal X is changing outside the process, not shown how.

How wait statements work?
... an alternative to a sensitivity list Note: a process cannot have both wait statement(s) and a sensitivity list Generic form of a process with wait statement(s) How wait statements work? Execute seq. statement until a wait statement is encountered. Wait until the specified condition is satisfied. Then execute the next set of sequential statements until the next wait statement is encountered. ... When the end of the process is reached start over again at the beginning. process begin sequential-statements wait statement wait-statement ... end process;

Forms of Wait Statements
wait on sensitivity-list; wait for time-expression; wait until boolean-expression; Wait on until one of the signals in the sensitivity list changes Wait for waits until the time specified by the time expression has elapsed What is this: wait for 0 ns; Wait until the Boolean expression is evaluated whenever one of the signals in the expression changes, and the process continues execution when the expression evaluates to TRUE

Signal assignment statements and wait for
p0 : process (A, B) begin Y <= A nand B after 10 ns; X <= transport A nand B after 10 ns; end process; p1 : process A <= '0', '1' after 20 ns, '0' after 40 ns, '1' after 60 ns; B <= '0', '1' after 30 ns, '0' after 35 ns, '1' after 50 ns; wait for 80 ns; Signal assignment statements and wait for Switching time of circuit p0 80nS A B X Y A pulse with a duration shorter than the switching time of the circuit (10nS) will be transmitted in transport. Recall waveforms , transport and inertial delay. Recall that default is intertial, as shown for signal X

Signal assignment statement
A pulse (5 nS) with a duration shorter than the switching time of the circuit (10nS) will be transmitted in transport. Inertial and Transport Delays

X Y entity DELAY is end DELAY; architecture RTL of DELAY is
signal A, B, X, Y : bit; begin p0 : process (A, B) Y <= A nand B after 10 ns; X <= transport A nand B after 10 ns; end process; p1 : process begin A <= '0', '1' after 20 ns, '0' after 40 ns, '1' after 60 ns; B <= '0', '1' after 30 ns, '0' after 35 ns, '1' after 50 ns; wait for 80 ns; end process; end RTL; X Y

Role of wait for in discarding signals
Waiting 30ns to start next assignment Waiting 50ns to start next assignment = 80 30ns 20ns entity DRIVER is end DRIVER; architecture RTL of DRIVER is signal A : integer; begin pa : process A <= 3, 5 after 20 ns, 7 after 40 ns, 9 after 60 ns; wait for 30 ns; A <= 2, 4 after 20 ns, 6 after 40 ns, 8 after 60 ns; wait for 50 ns; end process; end RTL; Discarded by the end of first assignment to A Discarded by the end of the second assignment to A. Time 30+50=80 has passed This slide explains the role of wait for to discard part of assignment statement

Differences between variables and signals
There are differences where declared and when updated 1. Where declared Local variables are declared and only visible inside a process or a subprogram. Signals cannot be declared inside a process or a subprogram. 2. When updated A local variable is immediately updated when the variable assignment statement is executed. A signal assignment statement updates the signal driver. The new value of the signal is updated when the process is suspended, as shown in last slide.

Signal assignment statement
Differences between variables and signals 3. Variables are cheaper to implement in VHDL simulation since the evaluation of drivers is not needed. Variables require less memory. 4. Signals communicate among concurrent statements. Ports declared in the entity are signals. Subprogram arguments can be signals or variables. 5. A signal is used to indicate an interconnect (net in a schematic). A local variable is used as a temporary value in a function description.

Signals versus variables
6. A local variable is very useful to factor out common parts of complex equations to reduce the mathematical calculation. 7. Right-hand sides: The right-hand side of a variable assignment statement is an expression. There is no associated time expression. The right-hand side of a signal assignment statement is a sequence of waveform elements with associated time expressions.

Signals and variables in timing diagrams
entity SIGVAL is port ( CLK, D : in bit; FF2, FF3 : out bit; Y : out bit_vector(7 downto 0)); end SIGVAL; architecture RTL of SIGVAL is signal FF1, SIG0, SIG1 : bit; begin p0 : process (D, SIG1, SIG0) variable VAR0, VAR1 : bit; Variables and signals on left begin VAR0 := D; VAR1 := D; SIG0 <= VAR0; SIG1 <= VAR1; Y(1 downto 0) <= VAR1 & VAR0; Y(3 downto 2) <= SIG1 & SIG0; VAR0 := not VAR0; VAR1 := not VAR1; SIG0 <= not VAR0; SIG1 <= not D; Y(5 downto 4) <= VAR1 & VAR0; Y(7 downto 6) <= SIG1 & SIG0; end process; Variables and signals on right

Timing of variables versus timing of signals
FF2 is old value of FF1 according to signal semantics p1 : process begin wait until CLK'event and CLK = '1'; FF1 <= D; FF2 <= FF1; end process; p2 : process variable V3 : bit; V3 := D; FF3 <= V3; end RTL; CLK D VAR0 VAR1 SIG0 SIG1 Y FF1 FF2 V3 FF3 Variable V3 changes at the same time as FF1, and so FF3 FF3 unlike FF2 MORAL: Signals are scheduled, variables change immediately

D c clk V3 Process Po WAIT Process 1 Process 2 D Q FF2 FF1 FF3 var0
p0 : process (D, SIG1, SIG0 variable VAR0, VAR1 : bit; begin VAR0 := D; VAR1 := D; SIG0 <= VAR0; SIG1 <= VAR1; Y(1 downto 0) <= VAR1 & VAR0; Y(3 downto 2) <= SIG1 & SIG0; VAR0 := not VAR0; VAR1 := not VAR1; SIG0 <= not VAR0; SIG1 <= not D; Y(5 downto 4) <= VAR1 & VAR0; Y(7 downto 6) <= SIG1 & SIG0; end process; c FF1 FF2 D D Q clk V3 FF3 Process 1 Process 2 Process Po p1 : process begin wait until CLK'event and CLK = '1'; FF1 <= D; FF2 <= FF1; end process; var0 p2 : process variable V3 : bit; begin wait until CLK'event and CLK = '1'; V3 := D; FF3 <= V3; end process; end RTL;

Using FF1, a signal, the old value is substituted
Using V3, a variable, the new value is substituted p1 : process begin wait until CLK'event and CLK = '1'; FF1 <= D; FF2 <= FF1; end process; p2 : process variable V3 : bit; V3 := D; FF3 <= V3; end RTL; CLK D VAR0 VAR1 SIG0 SIG1 Y FF1 FF2 V3 FF3 Compare FF2 (from signal change) and FF3 (from variable change)

wait until CLK'event and CLK = '1';
p0 : process (D, SIG1, SIG0) variable VAR0, VAR1 : bit; begin VAR0 := D; VAR1 := D; SIG0 <= VAR0; SIG1 <= VAR1; Y(1 downto 0) <= VAR1 & VAR0; Y(3 downto 2) <= SIG1 & SIG0; VAR0 := not VAR0; VAR1 := not VAR1; SIG0 <= not VAR0; SIG1 <= not D; Y(5 downto 4) <= VAR1 & VAR0; Y(7 downto 6) <= SIG1 & SIG0; end process; p1 : process begin wait until CLK'event and CLK = '1'; FF1 <= D; FF2 <= FF1; end process; p2 : process variable V3 : bit; begin wait until CLK'event and CLK = '1'; V3 := D; FF3 <= V3; end process; end RTL; SIG0 changes with D, no delay, in process 1 D, SIG0 and SIG1 are in sensitivity list FF1 takes old D V3 takes new D Input signals

Three architectures The same statements
variable V : integer; begin V := (B*C + D*E*F + G); Y <= A + V; Z <= A - V; end process; end RTL1; architecture RTL2 of TEMP is signal A, B, C, D, E, F, G, Y, Z : integer; signal V : integer; p0 : process (A, B, C, D, E, F, G) V <= (B*C + D*E*F + G); end RTL2; v calculated immediately The same statements entity TEMP is end TEMP; architecture RTL of TEMP is signal A, B, C, D, E, F, G, Y, Z : integer; begin p0 : process (A, B, C, D, E, F, G) Y <= A + (B*C + D*E*F + G); Z <= A - (B*C + D*E*F + G); end process; end RTL; architecture RTL1 of TEMP is Uses old value of v, because it is a signal First architecture has no variables Second architecture uses variable V Third architecture uses additional signal V Their operation is different because signal V is scheduled and variable immediately assigned

Signal Declarations Signals must not be declared inside a process or subprogram. Ports must always be signals. Models sub-system communication correctly.

Signals - Drivers Value holder for a signal.
Created when signal assignments schedule some value at some future time. Every signal has a separate driver. Can be thought of as a source for a signal. Driver maintains an ordered list of transactions. Recollect transaction is assignment made to a signal. Simulator uses the value of the signal stored in the driver.

Multiple Drivers Signals may be updated in more than 1 process at the same time. There may be more than 1 driver for the same signal, one for each process. The values assigned may be same or different. What to do if the values are different?

Multiple Drivers - Resolution
􀂃 Resolution function is the solution. 􀂃 This function resolves the value of the signal. 􀂃 This function must resolve all possible pairs of values that two drivers may assign. 􀂃 The signal being resolved is called the resolved signal. 􀂃 The resolution function can be attached to 􀂃 A signal directly or 􀂃 A data-type itself.

Homework Problem #1 Using the labels, list the order in which the following signal assignments are evaluated if in2 changes from a '0' to a '1'. Assume in1 has been a '1' and in2 has been a '0' for a long time, and then at time t in2 changes from a '0' to a '1'. entity not_another_prob is port (in1, in2: in bit; a: out bit); end not_another_prob; architecture oh_behave of not_another_prob is signal b, c, d, e, f: bit; begin L1: d <= not(in1); L2: c<= not(in2); L3: f <= (d and in2) ; L4: e <= (c and in1) ; L5: a <= not b; L6: b <= e or f; end oh_behave;

Homework Problem #2 Under what conditions do the two assignments below result in the same behavior? Different behavior? Draw waveforms to support your answers. out <= reject 5 ns inertial (not a) after 20 ns; out <= transport (not a) after 20 ns;

X. Sharon Hu Bob Reese Shankar Balachandran
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Transport and inertial delay Assignment statements

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Transport and inertial delay Assignment statements

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