1. ARM 7 Datapath

2. Has “BIGEND” input bit, which defines whether the memory is big or little endian Modes: ARM7 supports six modes of operation: (1) User mode (usr): the normal program execution state (2) FIQ mode (fiq): designed to support a data transfer or channel process (3) IRQ mode (irq): used for general purpose interrupt handling (4) Supervisor mode (svc): a protected mode for the operating system (5) Abort mode (abt): entered after a data or instruction prefetch abort (6) Undefined mode (und): entered when an undefined instruction is executed Major features Registers: 37 total registers: 31 general purpose (32 bit) and 6 status registers Only 16 general purpose registers are visible at any given time to the programmer The others are switched in to support IRQ/FIQ/SVC modes. R15 = PC ; R14 = return address A seventeenth register (the CPSR - Current Program Status Register) is also accessible. It contains condition code flags and the current mode bits and may be thought of as an extension to the PC.

3. Exception vectors LocationCause 0x00000000 Reset Supervisor 0x00000004 Undefined instruction Undefined 0x00000008 Software interrupt Supervisor 0x0000000C Abort (prefetch) Abort 0x00000010 Abort (data) Abort 0x00000014 -- reserved -- -- 0x00000018 IRQ IRQ 0x0000001C FIQ FIQ

4. Instruction Set All ARM7 instructions are conditionally executed, which means that their execution may or may not take place depending on the values of the N, Z, C and V flags in the CPSR. E.g.: code 0000 (EQual) causes the instruction to be executed only if the Z flag is set. This would correspond to the case where a compare (CMP) instruction had found the two operands to be equal. If the two operands were different, the compare instruction would have cleared the Z flag and the instruction will not be executed.

5. Instruction Set

6. Branch and link bit Branch addressing: Branch instructions contain a signed 2's complement 24 bit offset. This is shifted left two bits, sign extended to 32 bits, and added to the PC. The instruction can therefore specify a branch of +/- 32Mbytes. The branch offset must take account of the prefetch operation, which causes the PC to be 2 words (8 bytes) ahead of the current instruction. Branch with link: Branch with Link (BL) writes the old PC into the link register (R14) of the current bank. The PC value written into R14 is adjusted to allow for the prefetch, and contains the address of the instruction following the branch and link instruction. Note that the CPSR is not saved with the PC.

7. Data Processing Instructions S: Note the Set Condition Codes bit

8. Co-processor Instructions Co-processor Data Processing Co-processor “load” and “store” operations done similarly ARM7 takes nCPI LOW whenever it starts to execute a coprocessor (or undefined) instruction. (This will not happen if the instruction fails to be executed because of the condition codes.) Each coprocessor will have a copy of the instruction, and can inspect the CP# field to see which coprocessor it is for. Every coprocessor in a system must have a unique number and if that number matches the contents of the CP# field the coprocessor should drive the CPA (coprocessor absent) line LOW. If no coprocessor has a number which matches the CP# field, CPA and CPB will remain HIGH, and ARM7 will take the undefined instruction trap. Otherwise ARM7 observes the CPA line going LOW, and waits until the coprocessor is not busy.