1. M-CORE Introduction Topic Overview Comparison to Comp-Arch 1 topics Register Files Execution / Function Unit Elements Instruction Set / Execution Core Implementation General Implementation MMC2001 Other MCUs ARM7 THE PIC!!!!!!

2. Embedded Processors Embedded vs. Desktop Processors Advantages: Lower cost Optimized Instruction Set Lower Power consumption Smaller footprint Disadvantages: Slower clock speeds Less Processing power Applications Embedded Processors: Cell phones / pagers / PDAs DAQ Controls (Automotive, Industrial) “Smart” Media Desktop Processors: Desktop computers Notebook computers / Laptops

3. Overview

4. Register File User Programming Model 16 X 32 bit General Purpose Registers 32 bit Program Counter (PC) Carry Flag (C Bit) Supervisor Programming Model 16 X 32-bit alternate register file Processor and Global status registers (PSR/GSR) Vector base register (VBR) Exception saved Special Function Registers Five 32-bit supervisor scratch registers (SS0- SS4) Global Control Register (GCR)

5. Register File - Continued

6. Execution Unit Elements Hardware 32 bit ALU 32 bit Barrel Shifter Support Hardware for Multiplication Performance All instructions executed in single cycle except: Multiply Unsigned Divide Signed Divide

7. Instruction Execution 4 level pipeline Instruction Fetch Instruction Decode / Reg File Read Execute Reg File Write

8. Instruction Set Overview Instruction Types Data Byte / Bit Manipulation Logical Shifts (Rotates) Load and Store Control Conditional Arithmetic Special Monadic Instruction Format Dyadic Instruction Format Examples: ABS (Absolute Value – Monadic) XOR (Exclusive OR – Dyadic)

9. Exception Processing Exception Types Reset Misaligned access Access error Divide by zero Illegal instruction Privilege violation Trace Breakpoint Unrecoverable error Soft reset Interrupt Fast interrupt Hardware accelerator Trap instructions Exception Handling 1.Save PSR and PC to shadow registers (FPSR / FPC for fast interrupts, EPSR / EPC for all others) 2.Determine Vector Number of Exception 3.Determine Address of the First Instruction of Exception and Pass Control to Handler, Load PC and PSR with new values

10. Special Features Power Management Power Saving Instructions WAIT, DOZE, and STOP Compact die (2.2 mm 2 ) Minimized Logic and Routing Capacitance Gated Clocks Effective access to Internal and External Memory Hardware Accelerator Interface (HAI) Support for task acceleration by external hardware Data is Transferred between core and accelerator block by appropriate interface Acceleration blocks may be a counter, high speed multiply/accumulate or data encryption Debug Interface M-CORE Supports on chip emulation (OnCE) allowing a user to examine registers, memory or on-chip peripherals

11. Implementation M-CORE: More then just a CPU core MLB – M-CORE Local Bus PIG – Peripheral Interface Gasket PIG Bus – Peripheral Bus MIG – Module Interface Gasket EIM – External Interface Module PIE – PIG, Interrupt Control, EIM MIM – M-CORE Integration Module

12. Implementation–MMC2001 MMC2001 Includes: M-CORE 32 Bit Processor 256 K-Byte ROM 32 k-Byte SRAM with battery backup support External Interface Module 20 Address / 16 Data Lines Timer/Reset Module Time of Day timer Watchdog Timer Reset unit 2 Independent UART Modules 6 Independent PWM Modules Serial Peripheral Interface (SPI) Bus OnCE Debugger Module

13. M-CORE Key Advantages High Code Density 30% less memory than most 32 bit CPUs Low Power 1.8 to 3.6 V currently 0.9 V near future Several peripherals on chip Easy interface form the core to: communication hardware memory

14. M-CORE – Disadvantages Compared to other embedded processors, M-CORE really isn’t all it is hyped up to be! Motorola support is very poor Difficult to navigate website Poor documentation Motorola development tools are non-existent (or hard to find) Very poor selection MMC2001 MMC2107 Most features M-CORE prides itself on are “Future developments”

15. M-Core Compared - ARM M-COREARM Data Size32 Bit Speed50 MIPS130 MIPS Size2.2 mm 2.59 mm 2 Power Consumption.41mW/MHz.25mW/MHz Register File16 GP Registers

16. M-Core Compared - PIC M-COREPIC Number of Devices 2Nearly 100 Speed50 MIPS10 MIPS Today 30 MIPS Future Footprint144 Pin QFP8 Pin (DIP or SOIC) up to 80 Pin QFP CommentsDifficult to navigate documentation, Poor customer service Easy to navigate, Good customer service

17. M-Core Compared - PIC M-CORE (MMC2107) PIC (PIC18F458)dsPIC (dsPIC30F6014) Data Size32 Bit8 Bit16 Bit Speed31 MIPS10 MIPS30 MIPS ROM128K X 816K X 16144K RAM8K X 81.5K + 256 EEPROM 8K+ 4k EEPROM Peripherals10 bit ADC WDT SPI/SCI 10 bit ADC WDT UART/SPI/CAN 2.0 10 bit ADC WDT UART/SPI/I 2 C/CAN/ AC97/I 2 S Package144 QFP44 QFP80 QFP Clock input0 – 33 MHz0 – 40 MHZ0 – 10 MHZ Cost~$30.00~$10.00Future Product

18. QUESTIONS ?

19. References http://www.motorola.com/SPS/MCORE/ http://www.digikey.com http://www.arm.com/armtech/ARM7_Thumb?OpenDocument http://www.microchip.com/1010/index.htm Microchip Technologies 4 th Quarter 2001 Product Line Card