1. Camera Auto Focus Presentation 3, February 7 th, 2007 Team W1: Tom Goff (W11) David Hwang (W12) Kate Killfoile (W13) Greg Look (W14) Design Manager: Bowei Gai Project Goal: Design a low-power, small auto focus chip for a camera or other hand-held device

2. Status Last Time –Project chosen This Week C implementation Specifications defined Gate level design Floor plan In Process… –Structural Verilog –Low-power component selection Unfinished Schematic Layout Extraction, LVS, post-layout simulation

3. The Big Picture

4. Design Decisions 10 bit floating point representation SEEEEMMMMM Represent numbers from 8 to -8 (-11 = 3) No NAN or +/- Infinity Sequential multiplying Disable parts of the chip not in use

5. Adder Decisions Conditional sum adder Considering several low power full adder designs

6. C Implementation

7. Transistor Count ComponentFull Chip Count Registers600 Comparators1,650 FP multiplier1,500 Constant multipliers6,000 FP adder2,000 Subtractors3,000 Int to float logic2,000 Power control2,000 Rule logic6,480 Total~25,230

8. Size Estimate ComponentSize (µm²) Registers3,000 Comparators7,000 FP multiplier5,300 Constant multipliers25,000 FP adder9,500 Subtractors10,600 Int to float logic9,500 Power control9,500 Rule logic26,000 Total~105,400

9. Floor Plan

10. Metal Layers Metal 1Arbitrary Metal 2Arbitrary Metal 3Vertical Metal 4Horizontal

11. Next Steps Simulate structural Verilog Optimize logic Produce module schematics

12. Questions

13. References 14-transistor full adder –http://www.enformatika.org/data/v13/v13-15.pdf 12-transistor full adder –http://ieeexplore.ieee.org/iel5/10384/33117/01557317.pdf?tp= &arnumber=1557317&isnumber=33117