1. Architectural and System Synthesis SOURCES- DeMicheli Mark Manwaring Kia Bazargan Giovanni De Micheli Gupta Youn-Long Lin Camposano, J. Hofstede, Knapp, MacMillen Lin

2. Outline Motivation. Compiling language models into abstract models. Behavioral-level optimization and program- level transformations. Architectural synthesis: an overview.

3. Architectural Synthesis

4. Architectural Synthesis Problem Specification A sequencing graph A set of functional resources characterized by area and execution delay Constraints Tasks Place operations in time and space Determine detailed interconnection and control This is what we need to do in behavioral synthesis! :) Constraints include: area, cycle time, latency, and throughput. Area: number of modules/resources available or size of your silicon die. Cycle time: how fast your clock runs Latency: number of cycles for input data to result in a solution or result. Throughput: Amount of data that can be processed in a given amount of time (usually involves pipelining)

5. Behavioral Optimization

6. Resource Binding May have a pool of resources larger than required for problem Map a constrained set of resources to given operations Dedicated resources: each operation is bound to a single resource. 1.Resource pool: may include various kinds of multipliers (booth, array, etc) adders (tree, carry-lookahead, etc.) multipurpose units (ALUs, multiplier/divider, etc.) 2.Mapping a given set of resources to a set of known operations is one type of problem to solve. 3.Dedicated resource allocation is a one-to-one mapping.

7. Overview of Hardware Synthesis assign times to operations under given constraints reduce the amount of hardware, optimize the design in general. May be done with the consideration of additional constraints. assign operations to physical resources under given constraints

8. Architectural versus Logic Synthesis Transform behavioral into structural view. Architectural-level synthesi s: Architectural abstraction level. Determine macroscopic structure. Example of synthesis: major building blocks. Logic-level Logic-level synthesi s: Logic abstraction level. Determine microscopic structure. Example of synthesis: logic gate interconnection.

9. Synthesis and optimization

10. Example of HDL description of architecture diffeq { read (x, y, u, dx, a); repeat { xl = x + dx; ul = u - (3 * x * u * dx) - (3 * y * dx); yl = y + u * dx; c = x < a; x = xl; u = ul; y = yl; } until ( c ) ; write (y); }

11. Example of structures to implement this architecture Processes control and data

12. Principle of scheduling and allocation

13. Scheduling and Allocation adcbefgh 1 2 3 4

14. Internal representations Internal representation is design back-bone of synthesis Representations Parse tree Control-flow graph (CFG) Data-flow graph (DFG, SFG) Control/data-flow graph (CDFG) CDFG( contr ol data flow graph ) +1 +2 +3 *1*1 ab cd e g f h e=a+b; g=c+d; f=e+b; h=f*g;

16. Example of trade-off in architectural design

17. Architectural-level synthesis motivation Raise input abstraction level. 1.Reduce specification of details. 2.Extend designer base. 3.Self-documenting design specifications. 4.Ease modifications and extensions. Reduce design time. Explore and optimize macroscopic structure: Series/parallel execution of operations.

18. Design Space Exploration Arch I Arch II Arch III Delay Area We consider here totally different architectures

19. Stages of architectural-level synthesis 1.Translate HDL models into sequencing graphs. Behavioral-level 2. Behavioral-level optimization: 1.Optimize abstract models independently from the implementation parameters. Architectural 3. Architectural synthesis and optimization: 1. Create macroscopic structure: data-path and control-uni t. global 2. Consider area and delay information of the implementation. (on the global level)

20. Hardware and software compilation. software compilation. software compilation. hardware compilation. hardware compilation.

21. High Level Synthesis Compilation Flow

22. Compilation and behavioral optimization Software compilation: Compile program into intermediate form. Optimize intermediate form. Generate target code for an architecture. Hardware compilation Hardware compilation: Compile HDL model into sequencing graph. Optimize sequencing graph. Generate gate-level interconnection for a cell library.

23. Compilation Front-end: 1.Lexical and syntax analysis. 2.Parse-tree generation. 3.Macro-expansion. 4.Expansion of meta-variables. Semantic analysis: 1.Data-flow and control-flow analysis. 2.Type checking. 3.Resolve arithmetic and relational operators.

24. Parse tree example a = p +q r

25. Behavioral-level optimization Semantic-preserving transformations aiming at simplifying the model. Applied to parse-trees or during their generation. Taxonomy: 1. Data-flow based transformations. 2. Control-flow based transformations.

26. 1. Tree-height reduction. 2. Constant and variable propagation. 3. Common sub-expression elimination. 4. Dead-code elimination. 5. Operator-strength reduction. 6. Code motion. Data-Flow Based Transformations ( review ) We will illustrate each These are transformations done during compilation. There are similar transformations done during optimization to be discussed

27. Tree-height reduction Applied to arithmetic expressions. Goal Goal: Split into two-operand expressions to exploit hardware parallelism at best. Techniques: Balance the expression tree. commutativity, associativity and distributivit y. Exploit commutativity, associativity and distributivit y.

28. Example of tree-height reduction using commutativity and associativity x = ( a + (b * c ) ) + d x = (a +d) + (b * c)

29. Example of tree-height reduction using distributivity x = a * (b c d + e ) x = ( a b) (c d) + (a e);

30. Examples of propagation First Transformation type: Constant propagation: a = 0, b = a +1, c = 2 * b, a = 0, b = 1, c = 2, Second Transformation type: Variable propagation: a = x, b = a +1, c = 2 * a, a = x, b = x +1, c = 2 * x,

31. Sub-expression elimination Logic expressions: Performed by logic optimization. Kernel-based methods. We discussed with factorization Arithmetic expressions: Search isomorphic patterns in the parse trees. Example: a = x + y, b = a +1, c = x + y, a = x + y, b = a +1, c = a.

32. Examples of other transformations Dead-code elimination: a = x; b = x +1; c = 2 * x; a = x; can be removed if not referenced. Operator-strength reduction: a = x 2 ; b = 3 * x; a = x * x; t = x << 1; b = x + t; Code motion: for (i = 1; i  a * b) { } t = a * b; for (i = 1; i  t) { } Multiplication only once.

33. Control- flow based transformations 1. Model expansion. 2. Conditional expansion. 3. Loop expansion. 4. Block-level transformations. (will be discussed in more detail separately, presented on Friday) Next slides

34. Model expansion Expand subroutine and flatten hierarchy as the result. Useful to expand scope of other optimization techniques. Problematic when routine is called more than once. Example of model expansion: x = a + b; y = a * b; z = fo o (x; y); fo o (p; q) {t = q - p; return(t); } By expanding foo: x = a +b; y = a * b; z = y - x foo does subtraction

35. Conditional expansion Transform conditional into parallel execution with test at the end. Useful when test depends on late signals. May preclude hardware sharing. Always useful for logic expressions. Example: if else y = ab; if (a) {x = b + d; } else {x = bd;} a’ can be expanded to: x = a(b +d) +a’ bd and simplified as: y = ab; x = y +d(a +b) Moves conditionals from control unit to data path

36. Loop expansion Applicable to loops with data-independent exit conditions. Useful to expand scope of other optimization techniques. Problematic when loop has many iterations. Example of loop expansion: x = 0; for (i = 1; i  3; i ++) {x = x +1; } Expanded to: x = 0; x = x +1; x = x +2; x = x +3 Can use various variable semantics

37. What is architectural synthesis and optimization macroscopic structureSynthesize macroscopic structure in terms of building- blocks. Explore area/performance trade-offs: 1. maximum performance implementations subject to area constraints. 2. minimum area implementations subject to performance constraints. optimal Determine an optimal implementation. logic model Create logic model for data-path and control.

38. Design space and objectives in architectural synthesis Design space: Set of all feasible implementations. Implementation parameters: Area. Performance: Cycle-time. Latency. Throughput (for pipelined implementations). Power consumption

39. Three dimensional Design evaluation space

40. Hardware modeling 1. Circuit behavior: Sequencing graphs. 2. Building blocks: Resources. 3. Constraints: Timing and resource usage. Our methods and data structures have to model them for architectural design

41. What are Resources? 1. Functional resources: Perform operations on data. Example: arithmetic and logic blocks. 2. Memory resources: Store data. Example: memory and registers. 3. Interface resources: Example: busses and ports.

42. 1. Standard resources: Existing macro-cells. Well characterized (area/delay). Example: adders, multipliers,... 2. Application-specific resources: Circuits for specific tasks. Yet to be synthesized. Example: instruction decoder. Functional resources

43. Resources and circuit families Resource-dominated circuits. Area and performance depend on few, well-characterized blocks. Example: DSP circuits. Non resource-dominated circuits. Area and performance are strongly influenced by sparse logic, control and wiring. Example: some ASIC circuits.

44. Implementation constraints Timing constraints: Cycle-time. Latency of a set of operations. Time spacing between operation pairs. Resource constraints: Resource usage (or allocation). Partial binding.

45. Synthesis in the temporal domain Schedulin g: Associate a start-time with each operation. Determine latency and parallelism of the implementation. Scheduled sequencing grap h: Sequencing graph with start-time annotation. Result of scheduling

46. Example of Synthesis in the temporal domain ASAP Here we use sequencing graph

47. Synthesis in the spatial domain 1. Bindin g: Associate a resource with each operation with the same type. Determine area of the implementation. 2. Sharin g: Bind a resource to more than one operation. Operations must not execute concurrently. 3. Bound sequencing grap h: with resource annotationSequencing graph with resource annotation.

48. Example of Synthesis in the spatial domain First multiplier Second multiplier Third multiplier Fourth multiplier First ALU Second ALU Solution Four Multipliers Two ALUs Four Cycles

49. Binding specification Mapping from the vertex set to the set of resource instances, for each given type. 1. Partial binding: Partial mapping, design constraintgiven as design constraint. 2. Compatible binding: constraints of the partial binding.Binding which is satisfying the constraints of the partial binding. cont

50. Example of Binding specification Binding to the same multiplier

51. Estimation: area, latency, cycle time Resource-dominated circuits. Area = sum of the area of the resources bound to the operations. Determined by binding. Latency = start time of the sink operation (minus start time of the source operation). Determined by scheduling Non resource-dominated circuits. Area also affected by: registers, steering logic, wiring and control. Cycle-time also affected by: steering logic, wiring and (possibly) control.

52. What are the approaches to architectural optimization? Architectural Optimization is the Multiple-criteria optimization problem: area, latency, cycle-time. Determine Pareto optimal points: Implementations such that no other has all parameters with inferior values. Draw trade-off curves: discontinuous and highly nonlinear.

53. Approaches to architectural optimization 1.Area/latency trade-off, for some values of the cycle-time. 2. Cycle-time/latency trade-off, for some binding (area). 3. Area/cycle-time trade-off, for some schedules (latency).

54. Area/latency trade-off for various cycle times Area/Latency for cycle time=30 Area/Latency for cycle time=40 Pareto points in three dimensions

55. Area-latency trade-off Rationale: Cycle-time dictated by system constraints. Resource-dominated circuits: Area is determined by resource usage. Approaches: 1. Schedule for minimum latency under resource constraints 2. Schedule for minimum resource usage under latency constraints for varying constraints.

56. Summary on behavioral and architectural synthesis and optimization Behavioral optimization: Create abstract models from HDL models. Optimize models without considering implementation parameters. Architectural synthesis and optimization. Consider resource parameters. Multiple-criteria optimization problem: area, latency, cycle-time.

57. High-Level Synthesis Some authors treat architectural synthesis as part of high level synthesis In some systems there is no architectural synthesis but there are elements of specialized high-level synthesis specialized high-level synthesis: 1.For low power 2.For high testability 3.For high manufacturability

58. Low Power High Level Synthesis for Low Power

59. High Level Synthesis for low power Instructions Operations Variables Arrays signals specification Control Datapath Memory Operators, Registers, Memory, Multiplexor Control Scheduling Hardware allocation Memory inferencing Register sharing Control interencing for(I=0;I<=2;I=I+1begin @(posedge clk); if(fgb[I]%8; begin p=rgb[I]%8; g=filter(x,y)*8; end............ constraints high level synthesis RTL(register transfer level) architecture

60. Low Power design Power(Register) = switching(x)(C out, Mux +C in,Register )+switching(y) x (C out, Register +C in, DeMux ) switching(x)=switching(y) …. Power(Register)=switching(y) x C total

61. comparison of benchmarks for low power synthesis methods comparison of benchmarks for low power synthesis methods

62. Role of CDFG in High Level Synthesis CDFG Parsing Transformation Synthesis Structural RTL Behavioral Description This exists in any kind of high level synthesis

64. Design Flow of specialized high level synthesis systems Synthesizable (and executable) specification High level verification and design space exploration Synthesis / estimation / resynthesis Low level validation formal simulation Time-to-market often more important than chip area

65. Objective function 1 Main goals in classical approach 1.Minimum area Functional units, registers, memory, interconnect 2.Maximum speed Number of clock cycles Generally one parameter is set as a constrained and the other one is optimized

66. More sophisticated Objective functions for high-level and system design Additional goals in modern approaches More accurate estimation, such as Size of operands Sharing of hardware for similar operations (e.g. + and -) Testability Low power Power down, clock disabling Reliability Fault tolerance, self-test Controller

67. Other steps in HLS Chaining / multi-cycle operations Loop pipelining Retiming Memory design Reset, clock Interface design Estimation, integration with Logic Synthesis Real libraries (Higher level components)

68. Specification issues Timing I/O operations Cycle-fixed Superstate-fixed (pipelined) Free-floating (order only) Clocks Resets Registered outputs Loop pipelining

69. Behavioral Specification Languages Add hardware-specific constructs to existing languages HardwareC Popular HDL Verilog, VHDL Synthesis-oriented HDL UDL/I

70. VHDL synthesis tools RTL-synthesis FU allocation Limited register allocation Interconnect allocation Binding Logic and physical synthesis Behavioral synthesis HL Optimizations Scheduling RTL-synthesis

71. Chip Synthesis Now every stage of synthesis must take space into consideration Many issues do not exist in FPGA or architectural synthesis that use ready blocks but they exist in VLSI chip design. System on a chip

72. Layout, pins, power, temperature, Reliability, manufacturability, testability, test generation Chip synthesis

73. Layout and partitioning must be considered, must be iterated

74. Various models are used in the same synthesis process

76. Structure to layout

78. Software engineering

79. System Synthesis SYSTEM specification for a robot

80. Several ASIC chips are part of the entire system automatically designed

81. SYSTEM specification for a robot

82. Modern Experimental High-Level Synthesis System

83. System selects interactively or automatically the realization technology or mixture of them

84. To allow communication and integration, user’s feedback

85. System Synthesis System in chip versus system using a chip-set Variants of the robot system

86. Decomposition is not the same as partitioning System “knows” typical blocks and libraries of commercial components

87. Example of a System-on-a-Chip ProcessorMemory External Memory Interface IP Bus Master UART Wireless Bridge USB Everything in one chip – floorplanning and communication

88. SOC with PLDs ProcessorMemory External Memory Interface FPGA Bus MasterFPGA Wireless Bridge USB Everything in one chip – two FPGAs are inside, reconfigurable dynamically

89. Wafer Foundry System Houses/ IC Vendors (Fabless) Integrators Library/ IP Vendors (Chipless) EDA Vendors Paradigm Shift Move of EDA vendors to production

92. Essential Current and Open Issues in Design Automation Behavioral Specification Languages From Matlab to chip, from Prolog to chip, etc. Target Architectures Network on a chip, sensors and motion control integrated. Intermediate Representation For users to exchange, to understand the design better Operation Scheduling On the level of complex operations such as transforms or filters. Allocation/Binding On many levels of operations and processors Control Generation State machine optimization for large controllers New technologies, integrate FSM-logic-layout Still areas of active research

93. Future research areas in High Level Syntesis System level design Software-hardware system co-design Reuse Intellectual Property (IP) or Virtual Components (VC) More emphasis on verification currently often > 60% of design effort correctness by construction

94. Future Research: IP and Synthesis Authoring IP for Synthesis Synthesis utilizing IP Synthesizing IPs Executable Data Sheets

95. IP IP Wrapper More than just the Port Interface

96. Future Directions for system design Realistic Methodology Evolutional Transition from Current Practice Domain Specific IP-Centric As both Authoring Aid and Integrator Software Co-design and Code Generation Needs better collaboration of research universities and companies

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100. Exam Problem 1 Write set of equations for solving some type of equations by an iterative method Find Data Flow Graph for this set of equations Schedule Allocate Bind and share Design final data path Find control unit Optimize partitioning and communication Too long for one exam. Can be a take-home exam

101. Exam Problem 2 1.Allocate to time 2.Allocate to logic blocks 3.Design a complete controller 4.Design a controller for pipelined design

102. Exam Problem 3: Scheduling Set area constraint 2 multipliers 2 general-purpose ALUs Set the cycle time = latency of a multiplier Goal: minimize latency of circuit

103. Exam Problem 4 1.Give the set of functional resources: two multipliers, two ALUs. 2.Scheduling example with the constraints (two set constraints, then optimize the third) 3.We need to maintain the data dependencies. (e.g. vertex 6 must be scheduled at least one cycle after vertex 1.) 4.This is the same differential equation dataflow graph from a previous slide. 5.Edges that are not necessary to !show dependencies between vertices have been removed. 6.Complete this problem

104. Exam Problem 5: Binding

105. Exam Problem 5

106. Second Exam Problem 5: Competition for Students 1.The student with the smallest area gets a prize, the student with the smallest latency gets a prize. 2.Bring exam submission to the next lecture to be eligible for competition. 3.You are not required to give an optimal solution, since that may prove to be more difficult than can be done in a reasonable amount of time. Not for this year