1. Arithmetic Logic Unit (ALU) Lecture L9.3 Lab 10

2. ALU CB = carry_borrow flag Z = zero flag (Z = 1 if Y = 0)

3. MODULE alu interface([A3..A0],[B3..B0], [s2..s0] -> [Y3..Y0],CB,Z); TITLE '_____________________, _____________________, ___/___/03' DECLARATIONS " INPUT PINS " A3..A0 PIN; A = [A3..A0]; " 4-bit input A B3..B0 PIN; B = [B3..B0]; " 4-bit input B s2..s0 PIN; S = [s2..s0];" 3-bit control input " OUTPUT PINS " Y3..Y0 PIN; Y = [Y3..Y0]; " 4-bit output Y CB, Z PIN ISTYPE 'com';

4. " INTERMEDIATE NODES " C4..C0 NODE ISTYPE 'com'; " internal carry vector Cin = [C3..C0]; " carry input vector Cout = [C4..C1]; " carry output vector " DEFINITIONS " E = !s2 & !s1 & s0;" E = 1 for subtraction. Bin = B $ E; not = !A;" NOT A and = A & B;" A AND B or = _____;" A OR B xorr = ______;" A XOR B SD = A $ Bin $ Cin; " sum/difference (A + B, A - B)

5. EQUATIONS C0 = E; " E => CB0; (NOT B + CB0) = 2's complement of B. Cout = _______________________; " carry/borrow output vector CB = ___;" output carry/borrow Z = !Y3 & !Y2 & !Y1 & !Y0;" Z = 1 if Y = 0 when (S == 0) then Y = SD; " A + B when (S == 1) then Y = ___;" A - B when (S == 2) then Y = A;" A when (S == 3) then Y = ___;" B when (S == 4) then Y = not;" NOT when (S == 5) then Y = ___;" AND when (S == 6) then Y = ___;" OR when (S == 7) then Y = ___;" XOR END alu

6. Lab 10

7. A 1-Bit Register

8. A 4-Bit Register

9. MODULE reg4bit interface([D3..D0],clr,clk,load -> [Q3..Q0]); TITLE '_____________________, _____________________, ___/___/03' DECLARATIONS " INPUT PINS " clk PIN; " clock load PIN; clr PIN;" asynchronous clear D3..D0 PIN;" 4-bit input D = [D3..D0]; " OUTPUT PINS " Q3..Q0 PIN ISTYPE 'reg buffer'; " 4-bit output Q = [Q3..Q0]; " 4-bit reg output vector EQUATIONS Q.C = clk; Q.AR = clr; Q.D = ______________________; END

10. Lab 10

11. MODULE lab10 TITLE '____________________, ___________________, ___/___/03' DECLARATIONS hex7seg interface([D3..D0] -> [a,b,c,d,e,f,g]); d7L FUNCTIONAL_BLOCK hex7seg; d7R FUNCTIONAL_BLOCK hex7seg; alu interface([A3..A0],[B3..B0], [s2..s0] -> [Y3..Y0],CB,Z); alu1 FUNCTIONAL_BLOCK alu; reg4bit interface([D3..D0],clr,clk,load -> [Q3..Q0]); W FUNCTIONAL_BLOCK reg4bit; status FUNCTIONAL_BLOCK reg4bit;

12. " INPUT PINS " clk PIN 74;" clock clr PIN 70;" clear PA3..PA0 PIN 11,7,6,5;" Left Switches S6 - 1..4; PA = [PA3..PA0]; alusel2..alusel0 PIN 3,2,1;" alu select alusel = [alusel2..alusel0];

13. " OUTPUT PINS " C, Z PIN 35,36 ISTYPE 'com'; " carry and zero flags PD3..PD0 NODE ISTYPE 'reg'; " 4-bit reg output PD = [PD3..PD0]; PW3..PW0 NODE ISTYPE 'reg'; " 4-bit reg output PW = [PW3..PW0]; LD3..LD0 PIN 40,41,43,44 ISTYPE 'reg'; " leds 13-16 LD = [LD3..LD0]; [a,b,c,d,e,f,g] PIN 57,58,61,62,63,65,66 ISTYPE 'com'; "Leftmost (tens) 7-segment LED display [aa,bb,cc,dd,ee,ff,gg] PIN 15,18,23,21,19,14,17 ISTYPE 'com'; " Rightmost (units) 7-segment LED display

14. EQUATIONS W.load = 1; W.clr = clr; W.clk = clk; W.[D3..D0] = _____________; status.load = 1; status.clr = clr; status.clk = clk; status.D0 = alu1.CB; status.D1 = alu1.Z; alu1.[A3..A0] = _____; alu1.[B3..B0] = _____________; alu1.[s2..s0] = [alusel2..alusel0];

15. C = status.Q0; Z = status.Q1; PD = PA; PW = W.[Q3..Q0]; LD = alu1.[Y3..Y0]; [a,b,c,d,e,f,g] = d7L.[a,b,c,d,e,f,g]; d7L.[D3..D0] = PD; [aa,bb,cc,dd,ee,ff,gg] = d7R.[a,b,c,d,e,f,g]; d7R.[D3..D0] = PW;

16. @radix 16; test_vectors([clk,alusel,PA] -> [PW,C,Z]) [.C.,0,7] -> [__,__,__]; [.C.,0,5] -> [__,__,__]; [.C.,1,6] -> [__,__,__]; [.C.,2,4] -> [__,__,__]; [.C.,3,3] -> [__,__,__]; [.C.,4,0A] -> [__,__,__]; [.C.,5,0C] -> [__,__,__]; [.C.,6,2] -> [__,__,__]; [.C.,7,0C] -> [__,__,__]; [.C.,0,6] -> [__,__,__]; END lab10