1. CS150 Fall 2000 Project Info By: Nan (Norman) Zhou

2. CS 150 - Fall 2000 - Introduction - 2 Voice Over a Shared Network Project 1 Project 2 Project 3 Project 4 Hello World!

3. CS 150 - Fall 2000 - Introduction - 3 Board Level Block Diagram Xilinx FPGA XC4010XL PC84 Package Bus DAC SRAM 64KB DATA[7:0] ADDR[15:0] A/D Converter Mic Speaker Where all your designs go Discrete parts on Prototype Board Wire Wrap Line Transmit/Receiver

4. CS 150 - Fall 2000 - Introduction - 4 High Level Ideal zStart With Digitized Voice Data from A/D converter zTransmit Data in Packets Over the Shared Bus yListen for traffic ySend only if there is no traffic on the bus yListen for collisions and retransmit if necessary zReceive Data Packets Over the Shared Bus zSend Received Data to D/A converter to Recreate Sound zBuffer Incoming and Outgoing Data in SRAM

5. CS 150 - Fall 2000 - Introduction - 5 Inside the FPGA FIFO SRAM UART IN UART OUT Main Control FSM Collision Audio In interface Audio Out interface Packet Logic

6. CS 150 - Fall 2000 - Introduction - 6 Project Break Down zComplete project in pieces/checkpoints zCheck Point 1 ySRAM Interface yFIFO zCheck Point 2 yUART Transmitter Receiver zCheck Point 3 yAudio Interfaces zCheck Point 4 yPreliminary Global Data-path and Control zFinished Project

7. CS 150 - Fall 2000 - Introduction - 7 Check Point 1 zSRAM interface. yGenerate Control signals (OE CE WE) for Asynchronous SRAM zFIFO yGenerate Pointer Addresses For Head/Tail of ring Buffer yKeep track of Buffer status (full, empty, half full) FIFO SRAM 64KB

8. CS 150 - Fall 2000 - Introduction - 8 Check Point 2 zUART Transmitter yTakes Parallel Data Input yConverts to Serial yOutputs Serial Data to Bus yLook for Collision and Abort Transmission When Appropriate zUART Receiver yReads Serial Data from Bus yConverts from Serial to Parallel ySends Data to Rest of the Design y* Must Super Sample Data From Asynchronous Bus UART IN UART OUT

9. CS 150 - Fall 2000 - Introduction - 9 Check Point 3 zAudio In from A/D yExpand Data Path to Take Data From A/D yWrite Data in FIFO Buffer in SRAM yShares Data line with SRAM zAudio Out to D/A yTake Data from FIFO Buffer yConvert Data to Serial Form yOutput to D/A chip Audio In interface Audio Out interface

10. CS 150 - Fall 2000 - Introduction - 10 Check Point 3, comments zPlease read the Specs for the A/D, D/A chips zUse the Pulse generator to generate input for test. yMAKE SURE you first measure the output Peak to Peak voltage before you hook it up to the A/D. it should be 2 V yAlso try to use a audible frequency much lover than the sampling rate. 400Hz or so should be good. zKeep you chips close together! Save space! yThere are more chips on the way zElectrolytic Capacitors have a specific pin for ground and a different one for Vcc

11. CS 150 - Fall 2000 - Introduction - 11 Check Point 4 zPacket Logic yReceive Logic xTake Data From UART xReconstruct Packet xInterpret Packet and Take Appropriate Action ySend Logic xTake Data from SRAM xConstruct Packet xSend to UART zYou are expected to show successful transmission of a packet for this checkpoint.

12. CS 150 - Fall 2000 - Introduction - 12 What is a Packet? z5 bytes of UART transmission z1 header, and 4 data samples zHeader has 2 bit control, 3bit destination, 3bit source. Header, comes from Dipswitch Time

13. CS 150 - Fall 2000 - Introduction - 13 Packet Logic zConstruct Packet from byte input, coming from either UART in or FIFO (SRAM) zSend Packet byte at a time to UART out or FIFO (SRAM) zDecode packet yLook at header yIs packet for me? Packet Logic

14. CS 150 - Fall 2000 - Introduction - 14 Network Protocol zAlways listen on the shared bus. (everyone picks up everything on the line) zFilter out packets that does not have you as a source in the packet logic. zTransmission policy (greatly reduces collision frequency) yBefore you transmit first check Packet Logic and UART to see if bus is being used. yIf bus is not used then wait a random amount of time before you start transmission yIf 2 stations happens to decide to start at the same time, they collide, the station with the first 1 in the transmission loses and backs off. yTo tell collision check to see if output is same as input on the shared bus.

15. CS 150 - Fall 2000 - Introduction - 15 Network Protocol Busy Idle When bus is busy no one else can start a new transmission Collision can only occur when more than one station wants to transmit when the bus is idle. Even then it only happens when they both decide to start at the same time

16. CS 150 - Fall 2000 - Introduction - 16 What actually happens in a Collision? zWhen TX is low the line is Driven low. zHowever when TX is high the Line is left floating, and the resistor pulls the line high zThis means that during a collision whoever is sending a zero always wins. zThe winner continues to send as if nothing ever happened zThe loser detects that the 1 it’s trying to send is not being sent on the wire. So it stops immediately and tries later. TX.L RX Shared Bus

17. CS 150 - Fall 2000 - Introduction - 17 Trace of data flow in Final project 1.Analog input voltage is converted to 8bit unsigned # 2.This 8bit DATA is written directly into the SRAM through the shared data line of A/D and SRAM z this is done by asserting the WE of SRAM during the time when RD is asserted for the A/D chip zThe Address for the write is provided by the FIFO for the out going data. 3.Data is read out of the SRAM 4 bytes at a time and put into the packet logic. A header byte is also added by taking input from the DIP SWITCH

18. CS 150 - Fall 2000 - Introduction - 18 Trace of data flow in Final project 4.The packet is sent to the UART out one byte at a time. If the bus is idle and there is no collision 5.DATA travels bit serially to another station and gets picked up by UART in. 6.The UART in then sends the data to the Packet Logic one byte at a time 7.Packet Logic decodes the packet z If the destination matches the station then send the 4 data bytes to the SRAM one at a time. zThe OUTPUT FIFO generates the address

19. CS 150 - Fall 2000 - Introduction - 19 Trace of data flow in Final project 8.Read DATA from SRAM zConvert from 8bit unsigned to 16bit 2’s compliment (note I did a lousy job of that from the schematic I gave you guys for checkpoint 3. I expect better from you for the final project) 9.Send the converted data to the D/A z(and hopefully voice comes out)

20. CS 150 - Fall 2000 - Introduction - 20 Miscellaneous info zMax bus bit rate, 250Kbps zSuper sampled clock rate 2MHz zVoice sampling, 8bit, 2KHz y8 x 2K = 16Kbps pure data rate zNetwork Bandwidth taken per voice stream yPure data rate plus… yUART overhead 2bits per 8 data bits yPacket 1 header byte per 4 data bytes yIdle time overhead for random wait time after bus idle zMany shared resources! Think hard about how to share them.

21. CS 150 - Fall 2000 - Introduction - 21 Happy Halloween!