1. 11/17/2005Comp 120 Fall 20051 O Fortuna O Fortune, just as the moon you vary your state always increasing or decreasing; the detestable life now difficult and then easy with your games sharpens poverty, power dissolves like ice. Often great and empty, your revolving wheel, an evil state, vain health always dissolving, concealing and veiled you also strive for me now by game, a lost shirt I guiltily take because of you. Often my health and my virtue are now contrary for me, affected and defective always in torment; In this hour without delay take the pulse of my heart, which through fate, she overthrows my strength: weep all of you with me.

2. 11/17/2005Comp 120 Fall 20052 17 November 5 classes to go No class on Tuesday 22 November Last 2 classes will be extra topics and exam review Interconnect and IO

3. 11/17/2005Comp 120 Fall 20053 Final Exam Regular written examinations are required at the end of each term in all courses numbered below 200, except those whose nature makes written examination unnecessary. Exceptions must have advance approval of the Provost. A final examination schedule is announced each semester, and no examination (except for laboratory sections) may be held at any time other than specified. No instructor shall give a quiz or assign a paper that is not a part of the equivalent of a current daily recitation within one week (five class days) preceding the final examination period. Final examinations for a full course should ordinarily cover two hours but should not exceed a period of three hours. Each student is required to subscribe his or her name to the following pledge or its equivalent on every paper: "I hereby certify that during this examination I have neither given nor received aid." The instructor will not report a grade for any student whose examination paper lacks this pledge. Instead, he or she will register "no pledge" on the class grade report that is sent to the Office of the University Registrar.

4. 11/17/2005Comp 120 Fall 20054 So…Doh! Our Final Exam will be Saturday 17 December from 4PM to 7PM in (I guess) Ph 265. Dean of Students says notify your Community Director if you need to stay late in the dorms

5. 11/17/2005Comp 120 Fall 20055 Interconnect: Busses

6. 11/17/2005Comp 120 Fall 20056 Goals of Interconnect 1.Modularity Everything doesn’t fit on a single chip (yet) Where to draw the lines? Minimize communication? Minimize cost? Maximize expandability? 2.Expansion More processors More memory More devices

7. 11/17/2005Comp 120 Fall 20057 Backplane Bus

8. 11/17/2005Comp 120 Fall 20058 Issues in Interconnect Physical Interface –Single wire –Multiple wires –Radio –Light Protocol –Sync/Async –Master/Slave –Access Control Time-Division Multiple Access Frequency-Division Multiple Access Code-Division Multiple Access

9. 11/17/2005Comp 120 Fall 20059 Dawn of the Dumb Bus: ISA & EISA ISA (Original IBM PC Bus) Just take control and data signals from the CPU chip, buffer, and call it a bus

10. 11/17/2005Comp 120 Fall 200510 Smarter Buses The function that buses serve is simple: –They allow movement of data from point to point via transactions –They define rules for initiating and completing these transactions (PROTOCOLS) Terminology –BUS MASTER: a module who initiates a bus transaction –BUS SLAVE: a module who responds to a bus request –BUS CYCLE: The period from when a transaction is requested until it is served

11. 11/17/2005Comp 120 Fall 200511 Typical Synchronous Bus Timing Why an asymmetric clock? 1.Double duty – data transitions on one edge, sampled on the other 2.Assures “hold times” 3.Asymmetric high/low phases maximizes transmission interval 4.Allows for several “round-trip” bus delays so that ringing can die down

12. 11/17/2005Comp 120 Fall 200512 A Simple Bus Transaction Master 1.Acquires bus 2.Asserts start, operation, and address 3.Waits for bus to answer Slaves 1.Monitors every start 2.Check address 3.If meant for me a.Look at bus operation b.Do operation c.Signal finish of cycle Bus 1.Monitors start 2.Count down 3.If no one answers before counter reaches 0, then “time out”

13. 11/17/2005Comp 120 Fall 200513 Multiple Bus Masters Problem: Acquiring the bus. How to become a bus master? Example: “Daisy Chain” Arbitration

14. 11/17/2005Comp 120 Fall 200514 Bus Arbitration Issues Fairness – Given uniform requests, bus cycles should be divided evenly among modules Bounded wait – There should be an upper bound on how long a module as to wait between requesting and receiving a grant Utilization – Arbitration scheme should allow for maximum bus performance Scalability – Fixed-cost per module (both in terms of arbitration H/W and arbitration time

15. 11/17/2005Comp 120 Fall 200515 Ethernet

16. 11/17/2005Comp 120 Fall 200516 USB Universal Serial Bus Provides power and signal A single host connects to multiple devices Devices are given 7 bit addresses when plugged in Controller polls them round-robin 1.5Mbit/s for USB 1, up to 486Mbit/s for USB 2. Hot pluggable Plug and Play

17. 11/17/2005Comp 120 Fall 200517 Firewire IEEE 1394 Serial bus plus power Multiple masters Up to 800Mbit/s Hot pluggable Plug and Play

18. 11/17/2005Comp 120 Fall 200518 Interrupts How does the CPU manage SLOW I/O devices? 1.Programmed I/O 2.Interrupt Driven I/O

19. 11/17/2005Comp 120 Fall 200519 Polling Advantages Simple No surprises Processor in full control Disadvantages Polling can waste lots of time

20. 11/17/2005Comp 120 Fall 200520 Interrupt Driven I/O Advantage CPU only bothered when actually needed Disadvantage Can occur at surprising or inconvenient times Have to save and restore state

21. 11/17/2005Comp 120 Fall 200521 MIPS Exceptions Reset Hardware Errors (Check, Bus Error, Cache Error) External Interrupt (6 inputs) Address Error Reserved Instruction TLB Miss System Call Breakpoint Trap Integer Overflow Floating Point Error Timer And a few more

22. 11/17/2005Comp 120 Fall 200522 Exception Processing 1.EPC gets address of faulty instruction or of next instruction depending on type of exception 2.Switch to kernel mode 3.Jump to a new location based on type of exception PC  FFFF FFFF BFC0 0000 for Reset PC  FFFF FFFF BFC0 0300 for Hardware error PC  FFFF FFFF BFC0 0380 for external interrupts PC  FFFF FFFF BFC0 0400 for … 4.Save registers 5.Examine the “cause” register to find out why you came here 6.Branch to code to do the right thing

23. 11/17/2005Comp 120 Fall 200523 Magnetic Disk Long term, nonvolatile storage Large, inexpensive, and slow Rotating platter(s) coated with magnetic material Use a movable read/write head to access

24. 11/17/2005Comp 120 Fall 200524 Magnetic Disk Organization Cylinder: All tracks under head with arm in a fixed position Read/Write time has 3 components Seek time to move the arm Rotational latency: wait for the desired sector to come by Transfer time: transfer bits

25. 11/17/2005Comp 120 Fall 200525 Typical Disk Times Average Seek: 8ms to 12ms –Sum of all possible seek / number of possible seeks –Locality reduces this to maybe only 25% of average number Rotational Latency: –At 5400 RPM  11 ms –At 7200 RPM  8 ms –At 10000 RPM  6ms Transfer time depends on: –Transfer size (typical 512 bytes) –Rotation speed –Recording density –Diameter –Typical values: 10 to 30MBytes per second

26. 11/17/2005Comp 120 Fall 200526 Classes to go 4