1. SPFD-Based Wire Removal in a Network of PLAs Sunil P. Khatri* Subarnarekha Sinha* Andreas Kuehlmann** Robert K. Brayton* Alberto Sangiovanni-Vincentelli* * UC Berkeley CAD Group ** IBM Research

2. Outline u Motivation u Network of PLAs u Multi-valued SPFDs u Wire Removal using SPFDs u Experimental Results u Conclusions and Further Work

3. Motivation u PLAs being rediscovered in DSM design u IBM Gigahertz processor u Single PLAs used for control circuitry u High performance u Ability to quickly modify circuit u Circuit implementation using network of PLAs u Crosstalk-immune u Low area overhead u High performance

4. Network of PLAs u Utilize medium-sized PLAs u 5-10 inputs, 5-10 outputs u 15-40 product terms u Several advantages u Each PLA is fast and compact u Immunity from cross-talk u Decompose circuit into such a network u Overall area overhead minimal

5. Network of PLAs..2 u Decompose netlist into a network of PLAs u Algorithm attempts to reduce wiring between PLAs u Each cluster is tested for size by minimizing and folding the PLA a g f d b c e

6. Network of PLAs..3 u Each PLA implements 10’s of standard cells

7. SPFDs u Sets of Pairs of Functions to be Distinguished (SPFDs) u Introduced by Yamashita in ICCAD96 u Context of FPGA design u Modified by Brayton in IWLS97 for use in logic networks u Introduced SPFDs for node simplification u SPFD based wire removal/replacement introduced in ICCAD98 u Selectively removing/replacing wires in the logic to decrease logic complexity

8. Multi-valued SPFDs u An SPFD F(y) on a domain Y  undirected graph (V, E) where each v  V corresponds to a unique minterm in Y.  An edge e = (v 1, v 2 )  E means that minterms v 1 and v 2 should have different functional values y y y y y y y y 1 0 2 3 4 5 6 7 y0y0 y1y1 y2y2 y3y3 y4y4 y5y5 y6y6 y7y7

9. Multi-valued SPFDs..2 u A function F(y) implements F = (V, E) if F(y) is a valid coloring of F, ie F(y 1 ) != F(y 2 ), (y 1, y 2 )  E u Chromatic number of an SPFD is the minimum number of values required to implement the SPFD

10. Binary SPFD-based Wire Removal y y y y y y y y 1 0 2 3 4 5 6 7 f a b c y y y y y y y y 1 0 2 3 4 5 6 7 y y y y 1 0 2 3 y y y y 4 5 6 7 y y y y y y y y 1 0 2 3 4 5 6 7 y0y0 y1y1 y2y2 y3y3 y4y4 y5y5 y6y6 y7y7 Logicfunction

11. Binary SPFD-based Wire Removal..2 u Current algorithm uses CODCs to block effect of changes CODC CODC CODC Node change propagation is limited to red nodes f b a c

12. Binary SPFD-based Wire Removal Algorithm Y X Consider node h. SPFD of h is h(Y) Remove g 2 to get new space Y = Y - g 2 g 1 and g 3 now re-implemented Project h(Y) to PI space, call this projection H(X) ^ Project H(X) back to Y space, to get h(Y), the new SPFD of h ^ ^ ^ h g1g1g1g1 g2g2g2g2 g3g3g3g3 Now implement new h based on h(Y) ^ ^

13. Faster Binary SPFD-based Wire Removal Algorithm Y X Consider node h. SPFD of h is h(Y) Instead, project h(Y) to an intermediate space Z, call this projection H(Z) h g1g1g1g1 g2g2g2g2 g3g3g3g3 Z Need not project h(Y) to PI space ! Potentially suboptimal results, but much higher efficiency Remaining computation as described in previous slide

14. Wire Removal for Network of PLAs u PLAs can be viewed as MV nodes u PLA network has a few outputs of high fanout u Compute MV-SPFDs of the fanout PLAs u Try to remove the target output wire block u Don’t block changes by don’t-cares of fanout u Fanout PLAs can be easily re-implemented h 1, h 2, h 3 g2g2g2g2 g1g1g1g1 g2g2g2g2 g1g1g1g1 H (multi-valued) H g2g2g2g2 g1g1g1g1

15. MVSPFD-based Wire Removal y y y y y y y y 1 0 2 3 4 5 6 7 f a b c y y y y y y y y 1 0 2 3 4 5 6 7 y y y y 1 0 2 3 y y y y 4 5 6 7 y y y y y y y y 1 0 2 3 4 5 6 7 y0y0 y1y1 y2y2 y3y3 y4y4 y5y5 y6y6 y7y7 MV-function

16. Experimental Results - Standard Cell u Use binary SPFDs u Try to assign SPFD edges to a selected subset of fanin nodes u If any remaining fanins have no SPFD edges, they can be removed u Sweep the network after fanin wire is removed u 20% wire reduction at the logic level u Now perform technology mapping into a Standard-cell based implementation

17. Experimental Results - Standard Cell u Benefits at logic level negated at physical level u Technology mapping negates these benefits u Could perform wire removal after technology mapping u But logic nodes are too simple u SPFD based wire removal results in very little improvement u But the situation is different for a network of PLAs u No technology mapping step u Hence wire removal benefits got at physical level too

18. Experimental Results - Network of PLAs Decompose script.rugged run WR

19. Conclusions and Further Work u Binary SPFD based wire removal u Not helpful for standard cell based design u Extremely effective for network of PLAs u Implement MVSPFD based wire removal u Expect improvements for network of PLAs u Changes don’t need to be blocked by CODCs of fanout nodes u Nodes are complex, so flexibility is large u Initial coding underway