1. 22 February 2001ATLAS MDT Electronics PDR1 The MROD The MDT Precision Chambers ROD Adriaan König University of Nijmegen

2. 22 February 2001ATLAS MDT Electronics PDR2 Contents System Overview MROD-0 Prototype MROD-1 Prototype Performance Study FE Parameter Loading & Initialization Names

3. 22 February 2001ATLAS MDT Electronics PDR3 System Overview 6 x MROD 1.28 Gbit/s S-Link to ROB TDC 1 TDC 18 CSM 18 x TDC 1 TDC 18 CSM 18 x Chamber Tower CSM-Link

4. 22 February 2001ATLAS MDT Electronics PDR4 CSM-MUX Functionality Serial to Parallel & Clock Domain Separator 40 Mbit/s Data/Strobe from TDC 18 x Serial to Parallel & Clock Domain Separator 40 Mbit/s Data/Strobe from TDC Separator (CSM-Link)  1 Gbit/s 1 Start bit 32 Data bits 1 Parity bit 1 Stop bit 35 bits @ 25 ns = 875 ns 1 Separator word (S) 18 TDC data words 19 words in 875 ns  87 MB/s S 1 18 CSM-MUX

5. 22 February 2001ATLAS MDT Electronics PDR5 TDC0, word 1 TDC2, word 4 TDC3, word 2 TDC0, word 1 TDC1, word 3 TDC2, word 5 TDC3, word 3 TDC3, word 0TDC2, word 0TDC1, word 0 TDC1, word 1 TDC1, word 2 TDC2, word 1 TDC2, word 2 TDC2, word 3 TDC3, word 1 Build events in a partitioned memory from TDC data fragments (tdc 1) 000…000 Separator word Skip (do not store) Check (do not store) MROD Function time (tdc 0) 000…000 TDC0, word 0

6. 22 February 2001ATLAS MDT Electronics PDR6 MROD Throughput MROD 1.28 Gbit/s (  128 MB/s) MROD input MROD output Average 5 hits per TDC + header + trailer = 7 words/event Per tower of 6 chambers max. 88 TDCs * 7  600 words/event (= 2.4 kB/event) Worst case est.: @ 100 kHz L1A rate  240 MB/s per MROD Calculation based on actual tower layout (J.Chapman): max. rate < 60 MB/s per MROD CSM-Link S-Link CSM-Link

7. 22 February 2001ATLAS MDT Electronics PDR7 MROD Form Factor 9 U VME board (single slot), 6 Input Links, 1 S-Link Output Optionally 2 extra Input Links with “extension” board to accommodate special towers with > 6 chambers Input and Output Link Interfaces on main board SHARC II (ADSP21160), 2.5 x faster than 21060 1 MROD Crate contains: 12 MRODs (12  Segments) Max. 4 MROD Extension Boards 1 Standard (?) Crate Master with Ethernet Interface (DetDAQ) 1 TTC-Rx Interface Module 1 Busy Module ?? 1 DCS Interface Module ?? @ 192 towers: 192/12 = 16 MROD Crates (1 per  Sector)

8. 22 February 2001ATLAS MDT Electronics PDR8 MROD Crate LDAQMROD … total... 12 x 6 CSMs TTCrx Interface Module ROD Busy Module ROB DAQ / DCS VME-bus One MROD Crate services 12 towers (e.g. one full  sector). In total 16 crates will be required for all MDT chambers. Some MRODs may have 7 or 8 input links via “slave” MROD input cards. From TTC system “TTC-bus” Network

9. 22 February 2001ATLAS MDT Electronics PDR9 MROD-0 Prototype MRODOUT SHASLINK PCISHARC MRODIN MCRUSH sorted TDC-data over SHARC Link

10. 22 February 2001ATLAS MDT Electronics PDR10 1 MB ZBT Memory SHARC FPGA Data FIFO Tetris Register Input Output FIFOControl Control/Status Error signaling 6 Sharc links @ 40 MB/s each FIFO Length FIFO MCRUSH MROD-0 Input Channel

11. 22 February 2001ATLAS MDT Electronics PDR11 MROD-0 Output Channel SHaSLINK PCI 9054 SHARC Altera 10K10A S-Link max. @ 160 MB/s 6 SHARC Links @ 40 MB/s each PCI bus

12. 22 February 2001ATLAS MDT Electronics PDR12 (SHARC)

13. 22 February 2001ATLAS MDT Electronics PDR13 MROD -1 Prototype Memory SHARC FPGA SHARC (2x) Memory FPGA 3x ( in total ) VME64x TTC Interface Memory SHARC FPGA Memory FPGA Sharc Links

14. 22 February 2001ATLAS MDT Electronics PDR14 SHARC-II

15. 22 February 2001ATLAS MDT Electronics PDR15 The ADSP-21060 and the ADSP-21160 SHARCs 40 MHz / 80  100 MHz CPU (SIMD mode) 512 KB / 512 KB internal memory 6 x 40 / 80  100 MB/s links. Throughput of all links simultaneously is 160 / 480  600 (?) MB/s, without disturbing the CPU. No handshaking on links, but hardware XON-XOFF protocol, 10 / 14 DMA channels Support for bus arbitration: at max. 6 SHARCs can be connected to a common bus without glue logic. Each SHARC can access the internal memories of each other SHARC. The SHARCs also provide support for a so-called host interface, which can act as an additional master on the common bus. Fast interrupt servicing due to the presence of shadow registers Two 40 Mbit/s / 40  50 Mbit/s (at max.) synchronous serial ports Can be booted via link 4

16. 22 February 2001ATLAS MDT Electronics PDR16 MROD-1 Form Factor 9 U VME board, 6 S-Links in, 1 S-Link out S-Link interfaces on daughter boards SHARC II (ADSP21160), 2 x faster than 21060 (3 for input, 2 for output processing) Altera APEX FPGAs, 200k gates TTC interface over special back plane VME64x interface Motherboard Output Input S-Link daughter boards

17. 22 February 2001ATLAS MDT Electronics PDR17

18. 22 February 2001ATLAS MDT Electronics PDR18 MROD-1 Status & Planning VHDL design of FPGAs finalized. MROD-1 modules available by July 2001. Tests/performance measurements at NIKHEF. Read-out system of BOL test-stand (5 MDTs) at NIKHEF with special TDC32 CSM-MUX. System integration tests with CSM, ROB and DAQ test set-up (possibly in test-beam).

19. 22 February 2001ATLAS MDT Electronics PDR19 MROD Performance Study MRODIN MROD MRODOUT CSM ROB CSM

20. 22 February 2001ATLAS MDT Electronics PDR20 MROD Emulation Hardware MRODOUTROBIN ROBSIM SHASLINKCRUSHSHASLINK PCISHARC S-Link (PCI-)interface to host PC Module type xxxxx SHARC-link CSMSIM SHASLINK 0 1 0 MRODIN (3x) MCRUSH 0 2 3 4 4 RoIRR RoIR/ T2DR RoID/ T2OD MROD-0 44 22 00 TDC- data fragment lengths sorted TDC- data sorted + merged TDC-data sorted TDC- data optionally double/triple MRODIN output thus simulating 2 or 3 MRODINs event fragment lengths via SHARC-link simulates future MROD-1 functionality Region-of-Interest Requests, Decision Records, etc., everything needed to run a ROBIN simulation 13

21. 22 February 2001ATLAS MDT Electronics PDR21 MRODOUTROBIN ROBSIMCSMSIMMRODIN MROD

22. 22 February 2001ATLAS MDT Electronics PDR22 MRODOUTROBIN ROBSIMCSMSIMMRODIN MROD Performance Study Results

23. 22 February 2001ATLAS MDT Electronics PDR23 MRODOUTROBIN ROBSIMCSMSIMMRODIN MROD Performance Study Results

24. 22 February 2001ATLAS MDT Electronics PDR24 MRODOUTROBIN ROBSIMCSMSIMMRODIN MROD Performance Study Results

25. 22 February 2001ATLAS MDT Electronics PDR25 MRODOUTROBIN ROBSIMCSMSIMMRODIN MROD Performance Study Results

26. 22 February 2001ATLAS MDT Electronics PDR26 MRODOUTROBIN ROBSIMCSMSIMMRODIN MROD Performance Study Results

27. 22 February 2001ATLAS MDT Electronics PDR27 MROD Performance Analysis Measured event rate for single output SHARC @ 40 MHz with 3 input channels: event rate  min(50,1000/(10 + #words-per-CSM/6) kHz. MROD-1 uses SHARC-II @ 80 MHz: both processing speed and bandwidth increase proportionately  event rate  100 kHz ? ‘Final’ MROD: SHARC-II @  100 MHz.

28. 22 February 2001ATLAS MDT Electronics PDR28 FE parameter loading/initialization TTC TDCs ASDs CSMMRODROB DCS MDT-DAQ JTAG routing: Mezzanine boards CSM Link

29. 22 February 2001ATLAS MDT Electronics PDR29 JTAG Usage Initialize/Set/Reset ASD/TDC/CSM parameters Reload CSM parameters and flash memory (if/when needed) Timing calibration sequence: 1: JTAG enables calibration pulses in the ASD 2: TTC signals the CSM to send a test pulse 3: TTC subsequently provides a calibration trigger  No calibration during regular data taking since JTAG clock (TCK) must remain turned off to avoidnoise in the ASDs.

30. 22 February 2001ATLAS MDT Electronics PDR30 MROD Names (NIKHEF and Univ.of Nijmegen) Henk Boterenbrood Peter Jansweijer Gerard Kieft Adriaan König Jos Vermeulen Thei Wijnen NN (Post-doc vacancy at Univ.of Nijmegen: www.hef.kun.nl/vac-postdoc.html)