1. Tera-Pixel APS for CALICE Progress 19 th January 2007

2. Recent Activity IDR Foundry –Deep P implant –Submission date changed! Logic layouts well underway –Slightly larger than initial predictions Pixel layouts in early stages –Example Capacitor technology change

3. Area Estimates (from 6 th Sept 06) 26 bits ~ 100um 19 registers ~ 50um Mask + sample Mux Logic + Buffering SRAM controller Mask: 8.5um per 16 channels Local data buffers for global readout Mask + sample Select logic Bidir SR: 8.2um per 10 cells SRAM controller ~16.5u~25.5u 50  80um

4. Logic layouts: Actual sizes SRAM bank 126um Rd/Wr 22um Latch 21um Mux ~33um SR ~ (50 micron row pitch)

5. Likely Pixel Arrangement

6. Pixel Layout

7. Capacitor Technology MIM capNWcap NW N+ DPW P Substrate Top Metal Metal 1 Metal 5 @ 150ns @ 300ns Final pulse height @ 150ns @ 300ns