1. Idongesit Ebong (1-1) Jenna Fu (1-2) Bowei Gai (1-3) Syed Hussain (1-4) Jonathan Lee (1-5) Design Manager: Myron Kwai Overall Project Objective: Design a chip as part of a system that accommodates the growing demand for radio frequency identification (RFID) technology while creating a quicker, more convenient shopping experience. Presentation #1: Smart Cart 525 Stage I: 19 Jan. 2005 Design Proposal

2. Status Project chosen Specifications defined  Verilog obtained/modified  Gate-Level Verilog  Test Benches  Schematic Design  Layout  Simulations

3. Our chip will: Take in an 8-bit product ID from RFID receiver to find product price from a lookup table Keep a running total price for items to be purchased (allows for addition/removal of items from cart) Calculate subtotal, tax, total, and take store coupons into account Use Rijndael encryption to securely transmit 32 bit store card information to store’s central computer About the Smart Cart 525

4. What exactly is RFID? RFID tag: Antenna attached to a microchip which contains a unique 32->2048 bit ID code. Tag listens for radio query and responds with its ID information, no power needed. Versatility of RFID technology makes this marketable for other purposes as well  Applications: aircraft manufacturing, consumer electronics, baggage tracking in airports “Virtually every company on Earth will be required to use RFID in one way or another to remain competitive in the global market.”

5. Why use this chip? Quicker Shopping, wait free Secure transactions with AES encryption Low-cost (counterexample: IBM and Cuesol’s “Shopping Buddy”) Low power consumption Easy to maintain, update prices when being recharged at base stations.

6. Alternative Designs Neural chip- Implement a chip in the motor cortex of the brain to control motor movements of the prosthetic limbs. Total workout machine- Optimize workout by keeping track of bodily functions. JPEG filtering Blood sugar monitor

8. Multiplier, adder: floating point vs. non-floating point  Decided on non-floating point (multiplier will be big enough already—tentatively 16x5) Encryption: AES vs. DES (and how many bits?)  Decided on 32-bit AES since AES is the new standard  Anything smaller than 32 bits not doable with Rijndael algorithm Speed vs. power, pipelining  Low power, low speed to save battery power. No pipelining. Bit width of I/O pins  RFID code (simplified to 8-bit) etc to make our project manageable Design Decisions

9. Problems & Questions Unsure about complexity of certain blocks, which held us back from deciding on final specifications Having trouble finding Verilog code, but making some progress Encryption: too many algorithms out there, had to narrow down and simplify (reduce number of bits) to fit the scope of this course

10. Rough Transistor Count Encryption~7000 Multiplier~4000 Logic~2000 Adder~500 SRAM~5120 Registers (inputs/outputs)~1200 Total~19,820