1. Hardware/Software Integration in Portable Systems Trevor Pering University of California Berkeley

2. Outline ¶Background: The InfoPad Project ·Energy Efficient Microprocessors ¸System Design Environment This talk describes several research projects over the last six years that have relied heavily on integrated hardware/software design.

3. InfoPad Overview Perform all computation in the network to minimize client energy dissipation Centralized Application Compute Server Wireless Basestation Internet Database InfoPad Workstation capabilities on a portable device! High-bandwidth radio connection

4. InfoPad Software Architecture Communicate through centralized server to provide transparent ‘wired’ semantics Speech Recognizer “PadServer” Wireless Basestation InfoPad Maintain state in the network, not on the Pad Transmit audio and raw bitmaps across the wireless link Web Browser Internet Example: Hand-held speech-enabled web-browser

5. InfoPad Hardware Flexibility Use hardware/software integration to provide energy-efficient high-level functionality Only header sent to microprocessor 10 MIPS μProcessor Control Statistics Reliability Debugging Entire packet routed to dedicated hardware RX Packet Packet Header Frame- buffer update Embedded software responsible for high-level functions Main data-flow handled by custom low-power ASICs Radio Frame Buffer

6. InfoPad Evolution Total Power: ~7 W High-level system design optimizes complete solution and drives new research Where did the power go? No local computation? Commercial radios Commercial DC/DC Inefficient implementation Intercom Energy- Efficient Processors InfoPad

7. Outline ¶The InfoPad Project: Energy-efficient integrated system design ·Energy Efficient Microprocessors: Dynamic Voltage Scaling ¸System Design Environment

8. Trade-off energy and speed through voltage to minimize energy consumed Dynamic Voltage Scaling (DVS) E  V 2 f max  (V-c)/V E  f max Energy ~ Work Speed

9. DVS vs. Fixed-Voltage Reduce both speed and voltage to minimize both power and energy 10x energy savings DVS: Voltage:3x Speed:10x Energy:10x Power:100x

10. DVS Project Charter Design microprocessor system to support low-power devices I/O operations independent of processor architecture SRAM lpARM I/O Dynamic Voltage Regulator Scale voltage of entire microprocessor system! lpARM Intercom General-purpose software controls system voltage

11. DVS Scheduling Framework Use real-time framework to constrain task voltage scheduling µProc. Speed Time StartDeadlineStartDeadline Idle time represents wasted energy Lower speed, Lower voltage, Lower energy Energy ~ Work Speed Work

12. DVS Scheduling Schedule all tasks so as to minimize system energy dissipation Similar to minimizing  x i 2 with constant  x i µProc. Speed Time S1S1 S2S2 S3S3 D2D2 D3D3 D1D1 W1W1 W2W2 W3W3 W1W1 Task runs faster to meet timing constraints

13. DVS Simulation Simulate run-time scheduler to fully understand voltage-scaling behavior Speed Time S1S1 S2S2 S3S3 D1D1 D3D3 D2D2 Task Variance Weather Interrupts User Input Cache Behavior Scheduling Overhead Intercom RealityTheory Implementation

14. Simulation Benchmarks Model accurate I/O interaction to evaluate effects of voltage scaling Audio Decryption Graphical UI MPEG Decode Run-Time Support Audio Decryption Graphical UI MPEG Decode Run-Time Support Intercom SPEC

15. Simulation Infrastructure Develop support environment to model complete software system GUI Run-time Scheduler Voltage Scheduler Application support libraries MPEG  Priority 80 GUI  Priority 23 MPEG  Priority 80 GUI  Priority 23 Speed  Priority { Frame_Start(deadline); Decode_MPEG_Frame(); Frame_Finish(); } { Frame_Start(deadline); Decode_MPEG_Frame(); Frame_Finish(); } Windowing Cryptography I/O Support lpARM MPEG

16. Simulation Run-Time Algorithm Relax scheduling constraints to schedule efficiently in real-time µProc. Speed Time S1S1 S2S2 S3S3 D2D2 D3D3 D1D1 W2W2 W3W3 W1W1 Present time Schedule all tasks as if they were currently runnable: O(n log n) Speed = Work / Time Execute W 1 because W 2 is not yet runnable O(n 3 )

17. Run-Time Scheduling Dynamics Periodically re-evaluate schedule to adjust for unforeseen events µProc. Speed Time Thread accomplishing more than expected, reduce speed Deadline exceeded, increase speed Higher-priority task Run faster to make up lost time Initial speed estimate Optimal schedule E(work) Workload calculated to be average of previous frames

18. Run-Time Execution Trace Simulate the entire system to measure overhead and effectiveness System Idle Voltage Scheduler MPEG Decoder Interrupt Handler Time Frame Deadlines μProcessor Speed Scheduling Overhead < 3%

19. Results: Run-Time Voltage Scaling Dynamic Voltage Scaling significantly reduces energy dissipation! Normalized to 3.3V fixed-voltage processor Combination of independent benchmarks Includes 10% DVS implementation overhead

20. Run-Time Performance Analysis Application characteristics strongly affect voltage scaling performance AudioMPEGGUI Software can automatically recognize and adjust for bi-modal GUI distribution 0 2x deadline Normalized to deadline at max processor speed

21. Beyond Dynamic Voltage Scaling Voltage scheduling framework can be applied to many different designs and technologies Speed Time S1S1 S2S2 S3S3 D1D1 D3D3 D2D2 Intercom DSP CPU mem Disk * + lpARM

22. Outline ¶The InfoPad Project: Energy-efficient integrated system design ·Dynamic Voltage Scaling: Software control to minimize energy ¸System Design Environment: Top-Down Microprocessor Design

23. The lpARM Project Combine diverse backgrounds to develop an energy-efficient microprocessor 0.6  m DVS ARM8 processor with 16 kB on-chip cache Speed:10 - 100 MHz Voltage:1.1 - 3.3 V Energy:0.18 - 2.2 nJ/cycle Power:1.8 - 220 mW Control & Software Processor Design Dynamic Voltage Regulator Trevor Pering Tom Burd Tony Stratakos Processor validation & optimization Silicon expected May 1999 SRAM I/O Dynamic Voltage Regulator lpARM

24. lpARM Top-Down Design Use top-down design flow to optimize and verify design Cycle-level Instruction Simulation VHDL/Layout Hardware Simulation ANSI C Functional Simulation =?=? Intercom Functional Specification lpARM Iterative design

25. lpARM Feature Specification Simulate high-level system to discover desired implementation features Energy-saving processor features: Dynamic speed control Execution cycle counter Low-power sleep mode Interrupt speed control … Functional Specification Scale voltage to minimize energy System Simulation

26. lpARM End-to-End Verification Compare inter-simulation results to verify end-to-end design Frame 1 Chk: 0x2dbf92c2 Frame 2 Chk: 0x32fe4cda Frame 3 Chk: 0x3aa0d4ac Frame 4 Chk: 0x93efa7c8 Frame 5 Chk: 0x28f4efa9 Frame 1 Chk: 0x2dbf92c2 Frame 2 Chk: 0x32fe4cda Frame 3 Chk: 0x3aa0d4ac Frame 4 Chk: 0x93efa7c8 Frame 5 Chk: 0x28f4efa9 Application-level frame checksum VHDL Simulation Functional Simulation Instruction Simulation Transistor Simulation Memory hierarchy coherency Strict cycle-level comparison lpARM SRAM =?=? Functional Specification lpARM

27. lpARM Application Evaluation Evaluate target applications to accurately represent system behavior Direct-mapped cache is very application sensitive Intra-group normalized to 32-CAM ‘DVS energy’ includes system performance

28. lpARM System-Level Optimization Evaluate the complete system early-on to direct architectural design Other parameters analyzed: Write-back/Write-through Allocation policy Write-buffer size Associativity

29. lpARM Design Summary Simulating top-down hardware/software design improves end result Scale voltage to minimize energy Intercom Control & Software Processor Design Voltage Regulator Hardware and software components combine to form a system solution Top-down Speed Time S1S1 S2S2 S3S3 D1D1 D3D3 D2D2 lpARM

30. Conclusion ¶The InfoPad Project Energy-efficient integrated system design ·Dynamic Voltage Scaling Software control to minimize energy ¸Top-Down Microprocessor Design Application-driven energy optimization Effective energy-efficient systems require complete top-to-bottom integrated design