1. Built-In Self-Test and Calibration of Mixed-signal Devices Wei Jiang Ph.D. Dissertation Proposal June 11, 2009 Advisor: Vishwani D. Agrawal Committee Members: Fa F. Dai Victor P. Nelson Adit D. Singh

2. Outline Overview Background Built-in Test and Calibration Approach Current Progress Future Work Conclusion 2Wei JiangGeneral Oral Examination

3. Overview Issues – Parameter deviation – Process variation Problem – Design variation-tolerant process-independent technique for mixed-signal devices Approach – Test and characterization of mixed-signal devices – Output calibration Wei JiangGeneral Oral Examination3

4. Mixed-signal Device Analog and digital circuitry Digital controllable Typical devices – Converters, digital-to-analog/analog-to-digital – Amplifier Wei Jiang4General Oral Examination

5. Testing of Mixed-signal Devices Defects and faults – Catastrophic faults (hard faults) – Parametric faults (soft faults) Test approaches – Functional test (specification oriented) – Structural test (defect oriented) Wei Jiang5General Oral Examination

6. Challenges Analog circuitry – No convincing fault models – Difficult to identify faults – Device parameters more susceptible to process variation than digital circuitry – Fault-free behavior based on a known range of acceptable values for component parameters Large statistical process variation effects in deep sub-micron MOSFET devices Wei Jiang6General Oral Examination

7. Process Variation Parameter variation in nanoscale process Yield, reliability and cost Feature size scaling down and performance improvement Effects on digital and analog circuitry – Analog circuitry more affected by process variation – Parameter deviation severed in nanoscale process – System performance degraded when parameter deviation exceeds beyond tolerant limits Wei Jiang7General Oral Examination

8. Outline Overview Background Built-in Test and Calibration Approach Current Progress Future Work Conclusion 8Wei JiangGeneral Oral Examination

9. Typical Mixed-Signal Architecture Wei Jiang9General Oral Examination

10. Mixed-Signal System Test Architecture Wei Jiang10 * F. F. Dai and C. E. Stroud, “Analog and Mixed-Signal Test Architectures,” Chapter 15, p. 722 in System-on-Chip Test Architectures: Nanometer Design for Testability, Morgan Kaufmann, 2008. General Oral Examination

11. Mixed-Signal System Test Architecture Digital system – Digital I/O – Digital signal processor (DSP) – TPG and ORA and test control unit – Digital loopback Mixed-signal system – DAC and ADC – Analog loopback Analog system – Analog circuitry – Analog signal I/O – Analog I/O loopback Wei JiangGeneral Oral Examination11

12. Test Criteria Digital circuitry test – Defect-oriented test – Defects cat be detected by wrong output response for specific test pattern Analog circuitry test – Specific-oriented test – Parameter deviations vs. the acceptable tolerant limit Wei Jiang12General Oral Examination

13. Typical Mixed-Signal Devices DAC – digital-to-analog converter – Digital inputs; analog outputs ADC – analog-to-digital converter – Analog inputs; digital inputs Digital Controlled Amplifier – Analog inputs/outputs with digital controlling inputs – Analog transfer function controlled by digital device, e.g. microcontroller – Gain/distortion/nonlinearity respond to digital controlling signal Wei Jiang13General Oral Examination

14. Existing Testing Approach Oscillation BIST LFSR-based TPG FFT-based BIST Wei Jiang14General Oral Examination

15. Linearity Problem LSB – least significant bit – The minimum measurement for of analog value – Represented by 1 digital bit Non-linearity Error – DNL – differential non-linearity – INL – integral non-linearity Wei Jiang15General Oral Examination

16. Non-linearity Error of ADC/DAC Wei Jiang16 Non-linearity error Non-linearity error General Oral Examination

17. Other Characteristics Frequency response – Bandwidth Noise – SNR – signal-to-noise ratio – SINAD – signal-to-noise and distortion ratio Offset, gain, harmonic distortion Intermodulation distortion Wei Jiang17General Oral Examination

18. Outline Overview Background Built-in Test and Calibration Approach Current Progress Future Work Conclusion 18Wei JiangGeneral Oral Examination

19. Typical Mixed-Signal System with DAC/ADC Wei Jiang19General Oral Examination

20. Proposed Test and Calibration Architecture Wei Jiang20General Oral Examination

21. Components Description Digital circuitry (including DSP) as BIST control unit – Test pattern generation (TPG) and output response analysis (ORA) Measuring ADC – First-order 1-bit Sigma-Delta modulator – Digital low-pass filter – Measuring outputs of DAC-under-test Dither DAC – Low resolution DAC – Generating correcting signal for calibration – Calibrated DAC for test of ADC-under-test ADC Polynomial Fix – Digital process to revise ADC output codes Wei JiangGeneral Oral Examination21

22. Testing Procedure Self-test of testing and calibrating components – Self-test of BIST control unit (including DSP, TPG/ORA) – Self-test of measuring ADC – Test of dithering DAC by measuring ADC Test of On-chip DAC – Ramp test of on-chip DAC – Characterizing on-chip DAC by DSP – Calibration of on-chip DAC by dithering DAC Test of on-chip ADC – Ramp test of on-chip ADC – Characterizing and fixing on-chip ADC outputs by DSP Wei Jiang22General Oral Examination

23. Faulty Mixed-Signal Circuitry Good circuitry – All parameters and characteristics are within pre- defined specified range Fault-tolerant factor – Post-fabrication and software-controllable – Fault-tolerant factor varies for different application – Trade-off between fault-tolerance of parameter deviation and calibration resolution Wei Jiang23General Oral Examination

24. Determine Faulty DAC/ADC Coefficients representing offset, gain and harmonic distortion exceeding specific limit Maximum INL error exceeding calibration range (depending on fault-tolerant factor) – ±4LSB for fault-tolerant factor 3 INL errors of all calibrated outputs must be within ±0.5LSB Wei Jiang24General Oral Examination

25. Device Test and Calibration During BIST – Test DAC/ADC with ramp signals – Measure response of each test code – Obtain INL error for each code – Characterize device by INL error After BIST – Determine faulty devices by deviation of parameters – Generate correcting signal/data (identical to INL error) for each code – Calibrate DAC/ADC output using correcting signal/data by removing INL error Wei Jiang25General Oral Examination

26. The ONLY Problem Storing all INL errors for every input code of DAC/ADC is impossible – Requiring huge amount of memory – Needing lots of access time to retrieve specific data from memory – Prohibiting cost Solution – Polynomial fitting – Storing several coefficients instead of all data Wei Jiang26General Oral Examination

27. Test Pattern Test pattern – Ramp code – Least value to most value – Testing time for each pattern depends on the converting speed of measuring ADC Single-tone and multi-tone test patterns can also be used Wei Jiang27General Oral Examination

28. Test of Digital Circuitry Conventional digital BIST technology LFSR-based random test; Scan-based deterministic test Digital loopback conducted Fault-free digital circuitry then used for mixed- signal test May be hardware- or software-based Wei Jiang28General Oral Examination

29. Measuring ADC First-order 1-bit sigma-delta ADC Perform self-test before any other mixed- signal test Make sure each components of sigma-delta ADC working Quantization noise Bit-stream output pattern Wei Jiang29General Oral Examination

30. Sigma-Delta Modulator Wei Jiang30General Oral Examination

31. Sigma-Delta Modulator (cont.) Advantage – Oversampling and noise-shaping – High resolution and linear results – Resolution depends on OSR (oversampling ratio) – Simple structure and low cost Disadvantage – Very slow converting speed – Bit-stream output pattern issue for low-order modulation – Requiring high-speed clock Higher order and/or multi-bit modulation Wei Jiang31General Oral Examination

32. Selection of Sigma-Delta Modulator Wei Jiang32 First-order Second-order Third-order 17-bit ENOB 104.1LSB Oversampling ratio (OSR) SNR (LSB) General Oral Examination

33. Digital Filter Sigma-delta ADC consists of sigma-delta modulator and digital filter Low-pass filter (LPF) Integrator Comb filter Wei Jiang33General Oral Examination

34. Dithering DAC Low-cost low-resolution DAC Better linearity output with DEM technique Must be tested by measuring ADC before test of on-chip mixed-signal devices Wei Jiang34General Oral Examination

35. Resolution of Dithering DAC Wei Jiang35 3 α =1 17bits Resolution of dithering-DAC (bits) Estimated DAC resolution (bits) Oversampling ratio (OSR) 2 General Oral Examination

36. Polynomial Fitting Algorithm Introduced by Sunter et al. in ITC’97 and A. Roy et al. in ITC’02 Summary: – Divide DAC transfer function into four sections – Combine function outputs of each section (S0, S1, S2, S3) – Calculate four coefficients (b0, b1, b2, b3) by easily-generated equations Wei Jiang36General Oral Examination

37. Third-order Polynomial Wei Jiang37General Oral Examination

38. Adaptive Polynomial Fitting Dynamically choose polynomial degree Low-order polynomial – Simple to design and implement – Less area and performance overhead – Large fitting error High-order polynomial – Better fitting results – More coefficients to store – Much more complicated polynomial evaluation circuitry design and heavy area and performance overhead Wei Jiang38General Oral Examination

39. Test and Calibration of On-Chip DAC Wei JiangGeneral Oral Examination39

40. Test and Calibration of On-Chip ADC Wei JiangGeneral Oral Examination40

41. General Mixed-Signal Test Variation-tolerant design Digital controlled BIST Digitalized TPG/ORA Self-testable measuring components Characterization of device-under-test by DSP Faulty circuitry determined by characterized parameters Coefficients of output fix/correction signals calculated by DSP Wei Jiang41General Oral Examination

42. Outline Overview Background Built-in Test and Calibration Approach Current Progress Future Work Conclusion 42Wei JiangGeneral Oral Examination

43. Publications W. Jiang and V. D. Agrawal, “Built-In Test and Calibration of DAC/ADC Using A Low-Resolution Dithering DAC,” NATW’08, pp. 61-68. W. Jiang and V. D. Agrawal, “Built-in Self-Calibration of On-Chip DAC and ADC,” ITC’08, paper 32.2. W. Jiang and V. D. Agrawal, “Built-in Adaptive Test and Calibration of DAC,” NATW’09, pp. 3-8. W. Jiang and V. D. Agrawal, “Designing Variation- Tolerance in Mixed-Signal Components of a System- on-Chip,” ISCAS’09, pp. 126-129. Wei Jiang43General Oral Examination

44. Progress Presenting a novel approach to test and calibration DAC/ADC Presenting a method to dynamically determine the order of curve fitting polynomial for INL errors Proved by Matlab simulation theoretically Applicable for digitally controllable mixed- signal devices Wei JiangGeneral Oral Examination44

45. Simulation of DAC Test General Oral Examination45 14-bit DAC 16K ramp codes INL error up to ±1.5LSB Indices of 14-bit DAC-under-test INL of 14-bit DAC (LSB) Wei Jiang

46. Simulation (Cont.) General Oral Examination46 Fitting results by different order polynomial Indices of 14-bit DAC-under-test INL of 14-bit DAC (LSB) Wei Jiang

47. Best-matching Polynomial General Oral Examination47Wei Jiang

48. Fitting Algorithm Third-order polynomial fitting algorithm Adaptive polynomial fitting algorithm Determination of best matching polynomial degree Wei Jiang48General Oral Examination

49. Measuring ADC / Dithering DAC Measuring ADC – First-order 1-bit Sigma-Delta ADC – Higher-order multi-bit Sigma-Delta ADC – Non-Sigma-Delta ADC – Digital low-pass filter Dithering DAC – Binary weighted DAC Wei Jiang49General Oral Examination

50. Current Tasks Modeling and hardware verification of proposed testing approach Programming of third-order polynomial fitting algorithm Implementation and optimization of digital polynomial evaluation circuit Design and verification of the whole test and calibration system Wei JiangGeneral Oral Examination50

51. Outline Overview Background Built-in Test and Calibration Approach Current Progress Future Work Conclusion 51Wei JiangGeneral Oral Examination

52. Future Tasks and Schedule Testability of measuring ADC (~2 months) Best matching polynomial (~2 months) At-speed characterization (~1 month) Dynamic Element Matching (~1 month) Other testing techniques (~2 months) Dissertation and defending (~2 months) Wei JiangGeneral Oral Examination52

53. Testability of Measuring ADC Measuring ADC must be self-testable Testability of Sigma-Delta modulator Problem – Using digital circuitry and DSP to test analog circuitry – Measuring ADC must tell faulty or healthy by itself – Test of measuring ADC must be done before test of all other mixed-signal components Wei Jiang53General Oral Examination

54. Best Matching Polynomial Degree determination of best matching polynomial Problem – Find cut-off degree of INL errors – Higher-order polynomial brings heavy hardware overhead – Lower-order polynomial gives more fitting error Wei Jiang54General Oral Examination

55. At-Speed Characterization An approach to utilize idle time of DSP to re- calibrate mixed-signal devices Performance of analog components varies by environment, i.e. temperature, usage time Characterization during boot time may be inaccurate and need continuous revision during its lifetime Dynamic re-characterization of mixed-signal devices may reflect real condition of the devices and generate better results Wei Jiang55General Oral Examination

56. Dynamic Element Matching (DEM) Reduce non-linearity error of DAC/ADC Fault-tolerant for analog elements Approaches – Dynamically change/rotate matching elements to generate desired outputs for specific inputs – Reduce non-linearity of mismatching elements Disadvantage – Output pattern issue for low-order matching algorithm – Requiring high-speed clock Wei Jiang56General Oral Examination

57. Other Things… Frequency response test Noise test and removal Delay test Single-tone and multi-tone test Wei Jiang57General Oral Examination

58. Outline Overview Background Built-in Test and Calibration Approach Current Progress Future Work Conclusion 58Wei JiangGeneral Oral Examination

59. Conclusion A post-fabrication built-in test and calibration approach for mixed-signal devices is proposed This approach relies on digital circuitry and DSP for TPG/ORA and BIST control Digital circuitry is testable by conventional digital testing approaches and therefore guarantee the testability of analog circuitry The approach has been applied to test of DAC/ADC The same idea can be widely used for other digital- controlled mixed-signal devices Calibration on mixed-signal devices will significantly reduce defects, improve die yield and lower manufacturing cost Wei Jiang59General Oral Examination

60. Q&A THANKS Wei Jiang60General Oral Examination