1. Advances in Designing Clockless Digital Systems Prof. Steven M. Nowick nowick@cs.columbia.edu Department of Computer Science Columbia University New York, NY, USA

2. #2 Introduction Synchronous vs. Asynchronous Systems? Synchronous vs. Asynchronous Systems?  Synchronous Systems: use a global clock  entire system operates at fixed-rate  uses “centralized control” clock

3. #3 Introduction (cont.) Synchronous vs. Asynchronous Systems? (cont.) Synchronous vs. Asynchronous Systems? (cont.)  Asynchronous Systems: no global clock  components can operate at varying rates  communicate locally via “handshaking”  uses “distributed control” “handshaking interfaces” (channels)

4. #4 Trends and Challenges Trends in Chip Design: next decade  “Semiconductor Industry Association (SIA) Roadmap” (97-8) Unprecedented Challenges:  complexity and scale (= size of systems)  clock speeds  power management  reusability & scalability  “time-to-market” Design becoming unmanageable using a centralized single clock (synchronous) approach….

5. #5 Trends and Challenges (cont.) 1. Clock Rate:  1980: several MegaHertz  2001: ~750 MegaHertz - 1+ GigaHertz  2005: several GigaHertz Design Challenge:  “clock skew”: clock must be near-simultaneous across entire chip

6. #6 Trends and Challenges (cont.) 2. Chip Size and Density: Total #Transistors per Chip: 60-80% increase/year  ~1970: 4 thousand (Intel 4004 microprocessor)  today: 50-200+ million  2006 and beyond: towards 1 billion+ Design Challenges:  system complexity, design time, clock distribution  clock will require 10-20 cycles to reach across chip

7. #7 Trends and Challenges (cont.) 3. Power Consumption  Low power: ever-increasing demand  consumer electronics: battery-powered  high-end processors: avoid expensive fans, packaging Design Challenge:  clock inherently consumes power continuously  “power-down” techniques: complex, only partly effective

8. #8 Trends and Challenges (cont.) 4. Time-to-Market, Design Re-Use, Scalability Increasing pressure for faster “time-to-market”. Need:  reusable components: “plug-and-play” design  flexible interfacing: under varied conditions, voltage scaling  scalable design: easy system upgrades Design Challenge: mismatch w/ central fixed-rate clock

9. #9 Trends and Challenges (cont.) 5. Future Trends: “Mixed Timing” Domains Chips themselves becoming distributed systems….  contain many sub-regions, operating at different speeds: Design Challenge: breakdown of single centralized clock control

10. #10 Asynchronous Design: Potential Advantages Several Potential Advantages:  Lower Power  no clock  components use power only “on demand”  Robustness, Scalability  no global timing  “mix-and-match” variable-speed components  composable/modular design style  “object-oriented”  Higher Performance  systems not limited to “worst-case” clock rate

11. #11 Asynchronous Design: Some Recent Developments 1. Philips Semiconductors:  commercial use: 100 million async chips for consumer electronics: pagers, cell phones, smart cards, digital passports, automotive  3-4x lower power, less electromagnetic interference (“EMI”) 2. Intel:  experimental: Pentium instruction-length decoder = “RAPPID” (1990’s)  3-4x faster than synchronous subsystem 3. Sun Labs:  commercial use: high-speed FIFO’s in recent “Ultra’s” (memory access) 4. IBM Research:  experimental: high-speed pipelines, filters, mixed-timing systems Recent Startups: Fulcrum, Theseus Logic, Handshake Solutions, Silistrix

12. #12 Asynchronous CAD Tools: Recent Developments DARPA’s “CLASS” Program: Clockless Initiative (2003-07) Goals: - CAD tool: produce viable commercial-grade async tool flow - demonstration: a complex Boeing ASIC chip Participants:  Lead (PI): Boeing  Industrial participants:  Philips (via async incubated startup, “Handshake Solutions”)  Theseus Logic, Codetronix  Academic participants:  Columbia, UNC, UW, Yale, OSU Targets: cover wide “design space” – very robust to high-speed circuits Columbia’s role: (i) high-speed pipelines, (ii) CAD optimizations

13. #13 Asynchronous Design: Challenges Critical Design Issues: Critical Design Issues:  components must communicate cleanly: ‘hazard-free’ design  highly-concurrent designs: much harder to verify! Lack of Automated “Computer-Aided Design” Tools: Lack of Automated “Computer-Aided Design” Tools:  most commercial “CAD” tools targeted to synchronous

14. #14 What Are CAD Tools? Software programs to aid digital designers = “computer-aided design” tools  automatically synthesize and optimize digital circuits CAD TOOL Input: desired circuit specification Output: optimized circuit implementation

15. #15 Asynchronous Design Challenge Lack of Existing Asynchronous Design Tools:  Most commercial “CAD” tools targeted to synchronous  Synchronous CAD tools:  major drivers of growth in microelectronics industry  Asynchronous “chicken-and-egg” problem:  few CAD tools  less commercial use of async design  especially lacking: tools for designing/optmzng. large systems

16. #16 Overview: My Research Areas CAD Tools for Asynchronous Controllers (FSM’s) CAD Tools for Asynchronous Controllers (FSM’s)  “MINIMALIST” Package: for synthesis + optimization Other Research Areas: Other Research Areas:  CAD Tools for Designing Large-Scale Async Systems  Mixed-Timing Interface Circuits:  for interfacing sync/async systems  High-Speed Asynchronous Pipelines

17. #17 CAD Tools for Async Controllers MINIMALIST: developed at Columbia University [1994-]  extensible CAD package for synthesis of asynchronous controllers  integrates synthesis, optimization and verification tools  used in 80+ sites/17+ countries (being taught in IIT Bombay)  URL: http ://www.cs.columbia.edu/async Includes several optimization tools:  State Minimization  CHASM: optimal state encoding  2-Level Hazard-Free Logic Minimization  Verilog back-end Key goal: facilitate design-space exploration

18. #18 Example: “PE-SEND-IFC” (HP Labs) Inputs: req-send treq rd-iq adbld-out ack-pkt Outputs: tack peack adbld 0 1 2 7 3 4 5 6 8 9 10 req-send+ treq+ rd-iq+/ adbld+ adbld-out+/ peack+ rd-iq-/ peack- adbld- tack+ adbld-out- treq- rd-id+/ adbld+ adbld-out+/ peack+ rd-iq-/ peack- adbld- tack- adbld-out- treq+ ack-pkt+/ peack+ tack+ ack-pkt- treq-/ peack- tack- treq-/ tack- treq+/ tack+ ack-pkt+/ peack- tack- adbld-out- treq- ack-pkt+/ peack+ req-send-/ -- adbld-out- treq+ rd-iq+/ adbld+ From HP Labs “Mayfly” Project: B.Coates, A.Davis, K.Stevens, “The Post Office Experience: Designing a Large Asynchronous Chip”, INTEGRATION: the VLSI Journal, vol. 15:3, pp. 341-66 (Oct. 1993)

19. #19 EXAMPLE (cont.): Examples: Design-Space Exploration using MINIMALIST: optimizing for area vs. speed

20. #20 CAD Tools for Large-Scale Asynchronous Systems Target: - synthesize distributed control - 1 controller per functional unit Target Architecture: RegisterRegister FunctionalUnit FunctionalUnit FunctionalUnit Start Loop C< 0 B:=2dx+dx C:=X<a M:=U*X1 Endloop End X:=X+dx C:=X<a Input Specification: = “Control Data-flow Graph” control unit Ctrlr 1 Ctrlr 2 Ctrlr 3 [Theobald/Nowick, IEEE Design Automation Conf. (2001)]

21. #21 Mixed-Timing Interfaces Asynchronous Domain Synchronous Domain 1 Synchronous Domain 2 Goal: provide low-latency communication between “timing domains” Challenge: avoid synchronization errors Goal: provide low-latency communication between “timing domains” Challenge: avoid synchronization errors Asynchronous Domain

22. #22 Mixed-Timing Interfaces: Solution Asynchronous Domain Synchronous Domain 1 Synchronous Domain 2 Async-Sync FIFO Sync-Async FIFO Mixed-Clock FIFO’s … developed complete family of mixed-timing interface circuits [Chelcea/Nowick, IEEE Design Automation Conf. (2001)] Solution: insert mixed-timing FIFO’s  provide safe data transfer Asynchronous Domain

23. #23 global clock NON-PIPELINED COMPUTATION: High-Speed Asynchronous Pipelines “datapath component” = adder, multiplier, etc. SYNCHRONOUS

24. #24 global clock SYNCHRONOUS ASYNCHRONOUS “PIPELINED COMPUTATION”: like an assembly line no global clock High-Speed Asynchronous Pipelines

25. #25 Goal: extremely fast async datapath components  speed: comparable to fastest existing synchronous designs  additional benefits:  dynamically adapt to variable-speed interfaces: voltage scaling!  “elastic” processing of data in pipeline  no clock distribution Contributions: 3 new async pipeline styles [SINGH/NOWICK]  MOUSETRAP: static logic  High-Capacity/Lookahead: dynamic logic Obtain multi-GigaHertz speeds Used by IBM, currently incorporated into Philips tool flow High-Speed Asynchronous Pipelines

26. #26 req N ack N-1 req N+1 ack N Data Latch Latch Controller done N Data in Data out Stage NStage N-1Stage N+1 En MOUSETRAP: A Basic FIFO (no computation) Stages communicate using transition-signaling: [Singh/Nowick, IEEE Int. Conf. on Computer Design (2001)]

27. #27 Stage N+1 logic delay Stage N Data Latch Latch Controller done N logic delay Stage N-1 logic delay req N ack N-1 req N+1 ack N “MOUSETRAP” Pipeline: w/computation “MOUSETRAP” Pipeline: w/computation Function Blocks: use “synchronous” single-rail circuits (not hazard-free!) “Bundled Data” Requirement:  each “req” must arrive after data inputs valid and stable

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29. #29 req N ack N-1 req N+1 ack N Data Latch Latch Controller done N Data in Data out Stage NStage N-1Stage N+1 En MOUSETRAP: A Basic FIFO Stages communicate using transition-signaling: 1 transition per data item! One Data Item